SMACD 2016 - Lisbon, Portugal - prgS

Technical Sessions


Sponsored by:

PRIME 2016 and SMACD 2016 Technical Session Programme:

TUESDAY, June 28th
10:20-12:00 Data Converters I
Room 02.1
Chair: Jorge Fernandes
10:20-10:40

A High Resolution Multi-Bit Incremental Converter Insensitive to DAC Mismatch Error

Biao Wang1, Sai-Weng Sin1, Seng-Pan U1,2, R. P. Martins1,3

1State-Key Laboratory of Analog and Mixed Signal VLSI, Dept. of ECE, FST, University of Macau, Macao, China; 2Also with Synopsys Macau Ltd; 3On leave from Instituto Superior Técnico / Universidade de Lisboa, Portugal

This paper presents a second order multi-bit incremental analog-to-digital converter with two-phase feedback DAC control logic, insensitive to capacitor mismatches and with enhanced performance in multi-bit implementation. Besides, the proposed technique eliminates the complexity of dynamic element matching and relaxes the Op-amp’s settling time. Behavioral simulations show that it can achieve 115.55 dB SNDR at 128 clock cycles using a 7-bit quantizer without dynamic element matching.

10:40-11:00

A Novel Analytical Model for the Static Behavior of a Monotonic-Switching Charge-Scaling ADC

Florin Burcea, Husni Habal and Helmut Graeb

Institute for Electronic Design Automation, Technische Universität München

A novel, complete analytical model is derived for the static behavior of a monotonic-switching differential chargescaling ADC in terms of capacitor variations. Expressions derived for the transition voltages significantly reduce the cost of ADC transfer curve simulation. Capacitor variations create no offset error. Full expressions are derived and linearized for the integral and differential nonlinearity errors. These expressions enable the calculation of the worst-case values in consideration of statistical process variations. The worst-case values provide suitable objective functions to consider in capacitor placement optimization.

11:00-11:20

Minimal Pre-charge technique implemented for Switched-Capacitor Pipeline ADC

Jia Sun and Timo Rahkonen

Dept. of Electrical and Information Engineering University of Oulu Oulu, Finland

Slew rate limitation is a major cause of nonlinear settling error in switched capacitor circuits. In this paper we present a simple charge-sharing solution, by pre-charging the load capacitors properly, the initial input voltage step is minimized. The technique is simulated in a SC pipeline residue amplifier, and it provides 5.4 dB (nearly 1 bit) improvement in the settling accuracy with no additional active components. Alternatively, the same performance can be achieved by 20-30% bias current reduction in the op-amps.

11:20-11:40

A Reconfigurable Calibration Method for Current-Steering DACs

Gonçalo Nogueira, Jorge Fernandes and Gonçalo Tavares

INESC-ID, Instituto Superior Técnico, Universidade de Lisboa, Portugal

A new calibration method for current steering DACs based on dynamically rearranging the switching sequence of the MSB current sources, also called switching-sequence postadjustment (SSPA) is presented. This calibration method conducts a search for the optimal switching sequence that maximizes any desired performance metric instead of generating it based on ad-hoc or heuristic arguments. An add-on to the calibration method based on the correction of the output current is also proposed. The proposed calibration method improves the INL up to 9 times and the ENOB up to 1.1 bit when compared to a state-of-the-art SSPA calibration method.

11:40-12:00

An 8bit Logarithmic AD Converter Using CrossCoupled Inverters and a Time-to-Digital Converter

Mauro Santos 1,2, Nuno Horta 1,2 and Jorge Guilherme 1,3

1 Instituto de Telecomunicações, Lisbon, Portugal;2 Instituto Superior Técnico, Lisbon, Portugal; 3 Escola Superior de Tecnologia de Tomar, Tomar, Portugal

This paper presents an 8bit logarithmic AD converter comprising two conversion elements. One of the elements is a time-to-digital converter with a linear transfer characteristic and another is a voltage-to-time converter with a logarithmic transfer characteristic comprising two cross-coupled inverters. Simulation results for transistor level and post layout extraction are presented and discussed for an implementation in the UMC 130nm technology. Transistor level simulation results agree well with the theoretical prediction and post layout simulation results closely following the transistor level simulation results.

10:20-12:00PLLs and DLLs
Room 02.2
Chair: Nuno Paulino
10:20-10:40

Wideband Chirp Generation Techniques in Digital Phase-Locked Loops

Dmytro Cherniak1, Salvatore Levantino1, Carlo Samori1 and Roberto Nonis2

1 Politecnico di Milano, Milan, Italy; 2Infineon Technologies, Villach, Austria

In this paper in-depth analysis and comparison of two popular FM techniques, namely, two-point modulation and pre-emphasis of the modulation signal are presented. Both modulation enhancement techniques were implemented in the time domain model of an all-digital phase-locked loop (ADPLL). Their performance is evaluated based on Matlab simulations for different type of chirps. Obtained results show that chirps with the period of 0.1ms and peak-to-peak bandwidth of 1GHz can be generated with linearity better than 1% by employing either of these techniques. Additionally, advantages of two-point modulation with respect to ADPLL building block requirements are demonstrated.

10:40-11:00

Analysis of Adaptive Predistortion in DTC-Based Digital Fractional-N PLLs

Salvatore Levantino, Luigi Grimaldi and Carlo Samori

Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milano, Italy

The adoption of digital-to-time converters (DTCs) along with coarse, or even single-bit, time-to-digital converters (TDCs) is known to substantially reduce jitter and power consumption of digital fractional-N PLLs. Beside these advantages, DTC-based PLLs enable an adaptive pre-distortion algorithm which mitigates the nonlinearity of the DTC and the nonlinearityinduced fractional spurs. This paper provides a novel analytical framework of this linearization algorithm and demonstrates a reduction of fractional-N in-band spurs by 25 dB in a 3.6-GHz digital PLL.

11:00-11:20

Analysis of Fractional-N Bang-Bang Digital PLLs using Phase Switching Technique

Tuan Minh Vo, Salvatore Levantino and Carlo Samori

Politecnico di Milano - Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Milan, Italy

The adoption of the digital/time converter (DTC) circuit in fractional-N phase-locked loops (PLLs) allows the realization of high-performance bang-bang digital PLLs suitable for wireless communications. In this paper, a general expression of the dynamic range required for the DTC is derived as a function of the order of the Delta-Sigma modulator driving the frequency-divider modulus. Based on this, it is shown how the combination of the DTC with the M-phase switching technique helps to relax the DTC dynamic range by a factor of M and reduce its nonlinearity. The effectiveness of the phase switching technique is demonstrated via behavioral-level simulation of a digital PLL in the case of first-, second-, and third-order Delta-Sigma modulator.

11:20-11:40

Design of Differential Delay Lines in Low Temperature Cofired Ceramics

Pablo Benet Colom1, Francisco Ramos1 and Javier Sieiro2

1Research & development and innovation department Francisco Albero S.A.U., FAE, Hospitalet del Llobregat, Spain; 2Radiofrequency department, University of Barcelona, UB, GRAF, Barcelona, Spain

In this paper, a 3D differential delay line fabricated using a low temperature cofired ceramic (LTCC) technology is presented. The main feature of this component is its high value of delay density per unit area when compared with other differential geometries such as meanders, edge-coupled lines or twisted pair lines. An increase of a factor of 6 in the delay density is demonstrated, whereas distortion, attenuation and return loss are kept inside reasonable values.

10:20-12:00Modeling & Layout Techniques I
Room 02.3
Chair: Franco Maloberti
10:20-10:40

A Compact Electro-optical VCSEL Model for High-Speed IC Design

Guido Belfiore, Mahdi Khafaji, Ronny Henker, Frank Ellinger

Chair for Circuit Design and Network Theory, Technische Universität Dresden, Helmholtzstrasse 18, 01069 Dresden, Germany

This paper presents an accurate yet compact model for vertical cavity surface emitting lasers (VCSEL), which can be extracted from simple DC and small-signal electro-optical measurements. Since VCSELs are the bottleneck of high-speed electro-optical transceivers, the model is essential in the design of high-speed laser drivers. VCSEL rate equations are used to describe the electrical to optical conversion in the laser, while non-linear parasitcs are modelling the VCSEL interface. The model is applied to a commercially available VCSEL and there is an excellent agreement between the simulated and measured eye diagrams at different data rates and bias currents.

10:40-11:00

Nonlinear Modelling of Automatic Gain Control Loops Considering Loop Dynamics and Stability

Mohammed El-Shennawy, Niko Joram and Frank Ellinger

Chair for Circuit Design and Network Theory, Technische Universität Dresden, 01062 Dresden, Germany

This work presents modelling aspects of automatic gain control (AGC) loops based on linear-in-dB variable gain amplifiers (VGAs). In these loops, the VGA control voltage is also an excellent received signal strength indicator (RSSI). The VGA gain is however nonlinearly related to the control voltage. Moreover, VGAs and detectors undergo nonlinear compression under high input amplitudes during settling transients. In this work, these effects are captured by a nonlinear model based on simple and readily available components from the "analogLib" and "functional" libraries in CADENCE design environment making it very easy and fast to build and simulate. The model is capable of verifying the AGC loop stability and capturing the loop dynamics with high accuracy compared to time consuming circuit level simulations. This provides insights into system level parameters such as AGC loop bandwidth, phase margin, settling time as well as estimating the AGC range and RSSI voltage vs. input power. Measurement results from a fabricated AGC prototype are in good agreement with simulation and modelling results thus validating the proposed modelling approach.

11:00-11:20

Architectural Modeling of a Single-Sideband Wireline Serial Data Transceiver for Multi-Drop I/O

Gain Kim and Yusuf Leblebici

Microelectronic Systems Laboratory, Swiss Federal Institute of Technology in Lausanne (EPFL), Lausanne 1015, Switzerland

This paper presents a wireline serial data transceiver (TRX) architecture employing a concept of singlesideband (SSB) modulation to transmit data over a multi-drop (MD) electrical link with deep notches. The proposed TRX utilizes channel notch as a filter to remove one sideband of the power spectrum of the upconverted signal, thereby reducing the bandwidth occupancy by half. After downconversion is performed by a mixer on the receiver (RX) side, the original baseband (BB) signal can be recovered without loss of any information as long as the upconverted signal does not experience severe distortion by other notches. Simulation results show that the proposed TRX can transmit up to 6.4-Gb/s data stream over a reference MD channel of which the first notch is located at 2.5-GHz without any equalization circuit, while conventional TRX with non-return to zero (NRZ) signaling requires CTLE and at least 5-tap DFE for data rate above 5-Gb/s, to open the eye on the receiver side.

11:20-11:40

Formal Verification of Mixed-Signal Designs Using Extended Affine Arithmetic

Carna Radojicic and Christoph Grimm

University of Kaiserslautern

The complexity and heterogeneity of today’s mixedsignal systems makes verification a challenge. A particular challenge is the sensitivity of analog parts to variations in parameters, inputs, or initial conditions. We present a methodology for formal verification of mixed-signal systems that verifies the impact of variations of parameters, inputs, or initial conditions on specified properties. Compared with state of the art, the proposed methodology can be integrated easily in existing design flows, handles analog and digital parts, and offers improved scalability. The method is applied on a third order ΣΔModulator for verifying the stability property. The results show that our approach is using one simulation run able to find the input sequence that could lead to the undesired system behavior. These values are often not trivial and most likely would never be detected by traditional simulation-based techniques.

11:40-12:00

Efficient Modeling of Complex Analog Integrated Circuits Using Neural Networks

Ramin M. Hasani1, Dieter Haerle2 and Radu Grosu1

1Institute of Computer Engineering, Vienna University of Technology, Vienna, Austria; 2KAI Kompetenzzentrum Automobil- und Industrieelektronik GmbH, Villach, Austria

This paper introduces a black-box method for automatically learning an approximate but simulation-time efficient high-level abstraction of given analog integrated circuit (IC). The learned abstraction consists of a non-linear autoregressive neural network with exogenous input (NARX), which is trained and validated from the input-output traces of the IC stimulated with particular inputs. We show the effectiveness of our approach on the power-up behavior and supply dependency of a CMOS band-gap reference (BGR) circuit. We discuss in detail the precision of the NARX abstraction, and show how this model can be used and implemented in testing of Analog ICs within the Cadence environment. By using our method one can automatically learn high-level abstractions of all the components of an Analog IC. This dramatically speeds up the transient simulation time of the Analog ICs.

10:20-12:00Analog circuit and layout synthesis
Auditório
Chair: Günhan Dündar
10:20-10:40

On-the-fly Exploration of Placement Templates for Analog IC Layout-aware Sizing Methodologies

Ricardo Martins, António Canelas, Nuno Lourenço and Nuno Horta

Instituto de Telecomunicações, Instituto Superior Técnico - ULisbon, Lisboa, Portugal

In this paper, a methodology for automatic generation of placement templates for analog integrated circuit (IC) design is proposed and targeted to state-of-the-art layoutaware circuit-sizing flows. The multi-objective optimization (MOO)-based placement templates generator (PTG) inputs a Pareto set of sizing solutions and outputs a set of optimal sizingindependent non-slicing B*-tree floorplan representations, that fit the current state of the optimization process and are used within the layout-aware methodology to generate the floorplan of the following tentative solutions. This innovative methodology combines the advantages of previous template-based placement approaches, due to its fast packing, with the optimization-based ones, presenting floorplan solutions with improved compactability through the complete evolution of Pareto set. Moreover, as the PTG runs in parallel with the layout-aware loop, it has no impact on the layout-aware execution time. Experimental results present solutions with 47% less area when compared to a multi-template layout-aware approach.

10:40-11:00

Power-Down Synthesis for Analog Circuits including Switch Sizing

Michael Zwerger, Gaurav Shrivastava and Helmut Graeb

Institute for Electronic Design Automation, Technische Universität München, Munich, Germany

In order to reduce the power consumption of a system-on-chip, analog circuits can be switched off when not needed with the help of power-down switches. The power-down synthesis task comprises the structural synthesis of the powerdown circuitry and switch sizing. A first approach for automatic structural synthesis was published recently. This paper completes the power-down synthesis task by an effective, efficient and very easy sizing heuristic. An optimum size for the powerdown switches is identified. The sizing approach is derived from exhaustive simulation results for three different amplifier circuits and a voltage-controlled ring oscillator. The variations in the power-on performance values, the power consumption during power-down mode, the power-on to power-down settling time and the power-down to power-on settling time are determined for different sizes of the power-down switches. From the simulation results, it can be concluded that the technology’s minimal switch size can be chosen for the switches. This simple sizing step completes state-of-the-art power-down synthesis with the missing sizing step.

11:00-11:20

Automated Analog IC Design Constraints Generation for a Layout-Aware Sizing Approach

André Ferreira, Nuno Lourenço, Ricardo Martins and Nuno Horta

Instituto de Telecomunicações, Instituto Superior Técnico - ULisbon; Lisboa, Portugal

This paper presents an approach to automatically generate circuit-level design constraints to a layout-aware sizing approach. The proposed approach is an enhanced version and implementation of an established method, based on pattern recognition and symmetry detection, and is integrated in the AIDAsoft electronic design automation (EDA) environment. The generation of constraints increases the automation of the design process and reduces the risk of errors, assisting the project designer during the design specification setup. The validity and effectiveness of the proposed approach is illustrated for the synthesis of classical circuit structures in the AIDAsoft environment.

11:20-11:40

Optimization of LDO Voltage Regulators by NSGA-II

Jesús López-Arredondo1, Esteban Tlelo-Cuautle1, Francisco V. Fernández2

1INAOE, Department of Electronics. Luis Enrique Erro No. 1, Tonatzintla, Puebla. México; 2IMSE-CNM, CSIC and Universidad de Sevilla, Sevilla, Spain

Two different low-dropout (LDO) voltage regulators are optimized by applying the Non-Dominated Sorting Genetic Algorithm II (NSGA-II). First, from a sensitivity analysis a set of design variables are selected to establish a reduced chromosome for performing multi-objective optimization by NSGA-II. The computed sensitivities are used to reduce the search spaces for the design variables included into the chromosome, so that the optimization process is accelerated. Second, a comparison between traditional and optimization-based design approaches is shown by considering 2 figures of merit (FoM). Finally, we list the results for optimizing 2 LDO voltage regulators for the 2 FoMs, and provide optimized sizes that are compared to traditional design.

11:40-12:00

Analog Layout Placement Exploiting Sub-block Shape Functions

Khaled El-Kenawy1, Inas Mohammed2 and Mohamed Dessouky1

1Mentor Graphics, Egypt, Cairo 11361, Egypt; 2ECE, Ain Shams University, Cairo 11517, Egypt

This paper presents an analog layout placement flow based on Satisfiability Modulo Theories (SMT). For each building sub-block, different layout realizations are generated with different aspect ratio. The flow exploits the sub-block shape functions to explore placements that fulfill the given placement constraints attached to the building sub-blocks, as well as the toplevel layout aspect ratio. For placement optimization, different variants are generated for each valid placement consisting of a group of sub-block aspect ratios. Solutions are chosen based on minimum area and verified by post-layout simulations. Using SMT algorithms guarantees generating a solution if one exists while maintaining a very rapid run time. A two stage single ended OTA design using a 65nm process is used to demonstrate the flow with post-layout results.

14:00-15:40IC Design I
Room 02.1
Chair: Jürgen Scheible
14:00-14:20

A Fully Synthesized Key Establishment Core based on Tree Parity Machines in 65nm CMOS

Hector Gomez, Oscar Reyes and Elkim Roa

Design Group of Integrated Systems CIDIC - Universidad Industrial de Santander, Bucaramanga, Santander, Colombia

This paper presents a low-area ASIC implementation of a fully-synthesized symmetric key establishment architecture based on tree parity machines (TPMs) in 130nm and 65nm standard-cell CMOS technologies. The proposed circuit architecture has a serial datapath with re-keying characteristic enabled by a proposed pseudo-random binary sequence (PRBS) generator based on variable-length linear-feedback shift register (LFSR). A circuit technique is proposed that enhances datapath access to add re-keying feature. Fully-synthesized results for 130nm and 65nm show an area consumption of 0.016mm2 and 4800μm2 respectively. Relative area and power consumption are studied by comparing synthesized TPMs with an implementation of a CRC16 error detection code used within security applications. Comparison is made through a proposed figure of merit that include the generated key length in order to show scalability of the architecture with the available technologies.

14:20-14:40

A Self-organization Approach for Layout Floorplanning Problems in Analog IC Design

Daniel Marolt1, Jürgen Scheible1, Göeran Jerke2 and Vinko Marolt2

1Reutlingen University, Robert Bosch Center, for Power Electronics, 72762 Reutlingen, Germany; 2Robert Bosch GmbH, Automotive, Electronics, 72762 Reutlingen, Germany

In analog layout design, chip floorplans are usually still handcrafted by human experts. Particularly, the nondiscrete variability of block dimensions must be exploited thereby, which is a serious challenge for optimization-based algorithmic floorplanners. This paper presents a fundamentally new automation approach based on self-organization, in which floorplan blocks can autonomously move, rotate and deform themselves to jointly let compact results emerge from a synergistic flow of interaction. Our approach is able to minimize area and wirelength, supports nonslicing floorplan structures, can consider fully variable block dimensions, accounts for a fixed rectilinear boundary, and works absolutely deterministic. The approach is innovatively different from conventional, top-down oriented floorplanning algorithms.

14:40-15:00

ESD Protection Characterization by an Extended Wunsch-Bell Plot

Patrick Schrey

Graz University of Technology, Institute of Electronics, Inffeldgasse 12/I, 8010 Graz, Austria

Extensive knowledge of the protection device’s behavior under electrostatic discharge stress is mandatory to characterize protective elements and systems. This paper gives a brief overview on different electrostatic discharge protection concepts, including general considerations on diverting stress, trigger mechanisms, and their limitations. The protection approaches have to be selected in conjunction with the operational signals to avoid malfunction, increased power consumption, or physical failure. The Wunsch-Bell model is extended by means of an additional axis incorporating the rise time to better characterize different protective circuitry from component- to system-level. This allows for more accurate prediction of system robustness possibly preventing costly re-designs.

15:00-15:20

Advanced Circuit Interface for Systems with Multiple Voltage Domains

Harry Kalargaris, John Goodacre and VasilisF. Pavlidis, "

Advanced Processor Technologies Group, School of Computer Science, University of Manchester

Multi-level voltage scaling is a highly effective technique for reducing power and matching required speed in an integrated circuit. However, additional circuitry is required at the interfaces of the circuit blocks which operate at different voltage levels. These circuits impose a significant delay overhead and can prohibit the use of multi-voltage scaling at specific critical paths. These paths often cross boundaries of blocks that can otherwise operate at a different supply voltage, eliminating the benefits of multiple voltage domains. A by-pass circuit is proposed to alleviate these timing issues and simultaneously support multivoltage scaling under specific operating conditions. The new circuit results in performance improvements of up to 89% and power reduction up to 52% compared to traditional level-up and level-down shifters in a 32 nm technology node. Furthermore, greater performance and power savings are demonstrated where more cells are being by-passed, such as the isolation cells.

15:20-15:40

4-phase resettable quasi-adiabatic flip-flops and sequential circuit design

Sachin Maheshwari, V. A. Bartlett and Izzet Kale

Applied DSP and VLSI Research Group, Department of Engineering, University of Westminster, London, W1W 6UW, United Kingdom

Resettable adiabatic flip-flops are essential in the design of adiabatic counters, thus, a comprehensive study for IECRL, PFAL and EACRL 4-phase quasi-adiabatic logic families have been done in this paper. In addition, a new resettable quasi-adiabatic flip-flop circuit is proposed for each of them. Using the non-resettable and the proposed resettable adiabatic flip-flops, a practical sequential circuit comprising of a 2-bit twisted ring counter is designed and the energy consumption, for four distinct states, at different ramping times is measured. The simulation results show that the energy consumption of the resettable counter is comparable with its nonresettable counterparts. Moreover, amongst the adiabatic logic used, the PFAL based implementation of both the non-resettable and the resettable counters exhibits the least energy consumption at all ramping times.

14:00-15:40Oscillators and PLLs
Room 02.2
Chair: Luís Oliveira
14:00-14:20

A low-power 64-84GHz frequency quadrupler based on transformer-coupled resonators for E-Band backhaul applications

Lorenzo Iotti, Andrea Mazzanti and Francesco Svelto

Department of Electrical, Computer and Biomedical Engineering, University of Pavia, Italy

This paper presents a BiCMOS mm-Wave frequency quadrupler for E-band wireless backhaul applications. The circuit is intended to be a building block of a low-phase-noise E-Band frequency synthesizer. The multiplier employs transformer-coupled resonators for GBW enhancement and single-ended-to-differential conversion. The measured prototype achieves 27% fractional bandwidth around 74 GHz, with only 7mW power consumption.

14:20-14:40

Design of a Low Phase Error Multiphase Clock Generator for Modern Wideband Receivers

Miguel D. Fernandes, Luis B. Oliveira, João Goes, João P. Oliveira

Centre of Technology and Systems (CTS) - UNINOVA, Dept. of Electrical Engineering (DEE), Universidade Nova de Lisboa (UNL), 2829-516 Caparica, Portugal

This paper presents the design of a multiphase clock generator that can be integrated in a current-mode wideband receiver. This block consists of a ring of dynamic transmissiongate flip-flops, which generates 8-phase clocks non-overlapped with 12.5% duty-cycle, from an external input clock at eight times the desired output frequency. The circuit is designed using CMOS 65 nm technology with 1 V supply. Simulation results, for 1 GHz output clock, show that the phase error is 0.045°, considering process and mismatch variations of the circuit, with a power consumption of 10 mW, allowing the receiver to achieve HR3;5 > 60 dB for more than 95% of the Monte Carlo runs.

14:40-15:00

A 1-2 GHz Low Phase-Noise Wide-band LC-VCO with Active Inductor based Noise Filter

Zaira Zahir and Gaurab Banerjee

Department of Electrical and Communication Engineering, Indian Institute of Science, Bangalore, KA 560012 India

A voltage controlled LC-oscillator (LC-VCO) has been designed in a 130 nm CMOS technology to cover a wide range of frequencies (1.0-2.0 GHz). With a 66 percent tuning range and a maximum KV CO of 240 MHz/V , it consumes 2.1 mW of power from a 1.2 V supply. An active inductor based noise-filter improves the phase-noise performance of the oscillator without much increase in the area. The oscillator phase-noise is -120 dBc/Hz at an offset of 1 MHz at a carrier frequency of 2 GHz. It can be used for cognitive radio and other wide-band and multi-band RF applications.

15:00-15:20

Analysis of Power Efficiency in High-Performance Class-B Oscillators

Luca Bertulessi, Salvatore Levantino and Carlo Samori

Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, P.zza Leonardo da Vinci 32, I-20133 Milano, Italy

This paper presents an analysis of power efficiency in LC voltage-controlled oscillators (VCOs). Three different class- B topologies are compared under different operating conditions, demonstrating that the CMOS oscillator embedding two tail resonators achieves the best power efficiency and, consequently, best phase-noise-versus-power trade-off. A 65-nm CMOS prototype in post-layout simulations achieves a phase noise of -159 dBc/Hz at 20-MHz offset from the 3.6-GHz carrier, while dissipating 4.5 mW from 1.2-V power supply and covering 21.8% tuning range.

15:20-15:40

Non-linear Model for Multiple Phase Ring Oscillators

Paula C. Pereira1,2, Luis B. Oliveira2,3, Jorge Fernandes2

1Instituto Politécnico de Castelo Branco, Portugal; 2 INESC-ID Lisboa, Instituto Superior Técnico, Universidade de Lisboa, Portugal; 3 - CTS-UNINOVA, DEE, FCT / Universidade Nova de Lisboa, Caparica, Portugal

We present a high-level non-linear model for a multiple phase ring oscillator (MPRO), in terms of circuit parameters. From this model we obtain equations for the oscillation frequency, phase and phase difference error, which provide useful guidelines for the design of MPROs. The theoretical results are confirmed by high-level and circuit level simulations in a four-phase ring oscillator.

14:00-15:40Biomedical Applications IC
Room 02.3
Chair: Catherine Dehollain
14:00-14:20

A numerical design of versatile microchambers for nsPEFs experiments

Maura Casciola1, Agnese Denzi2, Micaela Liberti1 and Francesca Apollonio1

1ICEmB at DIET, Sapienza University of Rome, 00184, Rome, Italy; 2Center for Life Nano Science at Sapienza, Istituto Italiano di Tecnologia, Rome, Italy

The emergence of nanosecond pulsed electric fields (nsPEFs) for intracellular electro-manipulation experiments implies the application of extremely short (ns) high intensity (MV/m) electric field pulses. Specific pulse generators and miniaturized applicators are necessary to properly deliver this category of voltage signals to biological loads. In this context, we propose the design of a versatile nsPEFs applicator, developed following the guidelines typical of microwave propagating systems. The designed microchamber is suitable for in vitro exposure to undistorted pulses with duration down to 1-3 ns during single and multi cell experiments. Further features are: high efficiency (above 0.95), high cell viability by the integration of microfluidic components, real time monitoring of the biological sample and of the pulse propagation. These features can be considered as designing rules for new nanosecond and sub-nanosecond applicators, to ensure experimental repeatability and reproducibility when the impact of propagation on pulse signals is no more negligible.

14:20-14:40

A floating high-voltage level-shifter with high area efficiency for biomedical implants

Michael Haas and Maurits Ortmanns

Institute of Microelectronics, University of Ulm, Ulm, Germany

A major problem in State-of-the-Art digital, floating level-shifters is, that they either require a large area when employing positive feedback, or lack accuracy with respect to the floating digital supply, if an open-loop solution is used. In order to reach accurate, floating, digital supply levels, while using the area efficient, static level-shifter topology, a control-loop for the reference current is introduced. Thereby process, temperature and time related variations are compensated and the adaptive reference can be distributed to an arbitrarily large array of level- shifters. The whole architecture has been simulated, layouted and manufactured in a standard 0.18 μm HV CMOS process. Simulation results show, that the design is capable of shifting digital signals from 0/3V to a floating 6/9V and -6/-9V domain with a delay of 250 ns and 150 ns respectively. By reducing the amount of high voltage transistors and utilizing low voltage diodes in the floating voltage domain, an area of only 65 μm x 33 μm per level-shifter can be realized. This is especially advantageous for the intended application in a multichannel neural stimulator, where many level-shifters are needed to switch the dedicated functions in the floating high voltage domains. The required bias current control-loop has a simulated power consumption of only 94 μW and requires an area of 137 μm x 97 μm.

14:40-15:00

Delta Compression in Time-multiplexed Multichannel Neural Recorders

Matteo Pagin, Michael Haas, Joachim Becker and Maurits Ortmanns

Institute of Microelectronics, Unversity of Ulm, Ulm, Germany

In this paper we analyze the effectiveness of a serial delta compression scheme for reducing data rate of neural signals in brain implanted systems. Due to their location neural implants have limited power budget in order not to damage the surrounding tissues. In an implant with a wireless communication link the data rate needs then to be reduced to meet the power requirements since the transmitter power consumption is often a dominating factor. In this paper we propose and analyze a digital delta compression scheme for multichannel implants which reduces the number of registers and offers more flexibility compared to the canonical scheme. Instead of subtracting from samples belonging to one channel we explore the possibility of using samples from different but correlated channels, this removes the need of storing previous samples for all channels. Synthesized and recorded data sets are used to investigate the effectiveness of the method together with a spike sorting program, to also evaluate the quality of the reconstructed signals.

15:00-15:20

A 4-Mode Reconfigurable Low Noise Amplifier for Implantable Neural Recording Channels

José Luis Valtierra Sánchez de La Vega, Ángel Rodríguez-Vázquez and Manuel Delgado Restituto

Institute of Microelectronics of Seville and University of Sevilla, Avda. Americo Vespucio s/n, 41092-Seville,SPAIN

In this paper a reconfigurable implantable low noise amplifier for the recording of neural signals is presented. It is comprised by low-power and noise efficient current reuse OTAs in its direct path. The proposed architecture allows for an active feedback to set the high-pass corner in place of the commonly used pseudoresistor. Bandwidth selectivity is achieved by cicuit reconfigurability which changes the pole frequencies of the system without impacting the total power consumption. Simulation results in AMS 0.18μm technology validate the proposed architecture in both nominal and corner process conditions with an estimated total power consumption of 454nW.

15:20-15:40

A Bio-Inspired Reconfigurable Architecture for Local Binary Descriptors

Selman Ergünay and Yusuf Leblebici

Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland

Limited resources of embedded devices and increased real time constraints have raised interest to the binary description methods over the floating-point ones such as SIFT and SURF in computer vision applications. Although many software applications of the binary descriptors are developed, there are few studies on their hardware implementations in the literature. Despite the fact that direct hardware implementation of the algorithms can enhance the performance of calculations, flexible architectures which are able to support new approaches remain still an issue. At this point, mimicking biological neural network which has naturally capable of extracting features can offer different insights to the problem. In this paper we propose a reconfigurable architecture and its’ hardware implementation for local binary description applications, inspiring from the biological neural network structures. Specifically, this architecture is based on the Cellular Neural Network (CNN), with two different types of cells which show either inhibitory or excitatory behaviour. Imposed restrictions on classical CNN architecture lead a multiplier-less area-efficient realization, while keeping the necessary flexibility. This network can be configured as an accelerator unit of the local binary descriptors in embedded vision applications.

14:00-15:40Power applications and energy management
Auditório
Chair: Giulia di Capua
14:00-14:20

An Improved Algorithm for the Analysis of Partially Saturated Ferrite Inductors in Switching Power Supplies

Giulia Di Capua, Nicola Femia and Kateryna Stoyka

Department of Information and Electrical Engineering and Applied Mathematics, University of Salerno, Fisciano (SA), 84084 ITALY

Ferrite inductors operation in partial saturation offers unexplored opportunities in reducing the size of magnetic parts and the power losses in High-Current-Ripple Switching Mode Power Supplies (HCR SMPSs) using SiC and GaN devices. A reliable prediction of the inductor current ripple is required to exploit such opportunities. A new method for ripple analysis of saturated inductors has been recently proposed, allowing the investigation of effective SMPS design solutions with minimum size inductors. An extension of such method is herein presented, allowing design investigations for the reliable use of partially saturated ferrite inductors in HCR SMPS applications. Simulation results and experimental tests fully validate the proposed method.

14:20-14:40

A specialized time-step control strategy for fast simulation of switching power electronic circuits

Johann Wilhelm and Werner Renhart

Institute for Fundamentals and Theory in Electrical Engineering, Inffeldgasse 18, 8010 Graz, AUSTRIA

Simulation times of electric circuits containing switching power supplies not only depend on the algorithms used for solving the network equations but also on the choice of the time-step-control strategy. While generic simulation packages use the estimated truncation error to find the optimum time step, in this work a more specialized approach was followed. After studying the analytic solution and the simulation results of a circuit utilizing a pulse-with-modulation scheme it was found, that the switching intervals form adequate time-steps. To prove this, a basic simulation software was implemented and several simulations were conducted. Finally, the simulation accuracy was improved by introducing additional time-steps and impact on the convergence speed and memory consumption was studied.

14:40-15:00

Impact of Semiconductors on the Performance of Wireless Power Transfer Systems

Giulia Di Capua1, Nicola Femia1, Gianpaolo Lisi2 and Giovanni Petrone1

1Department of Information and Electrical Engineering and Applied Mathematics, University of Salerno, Fisciano (SA), 84084 ITALY; 2Kilby Laboratories - Silicon Valley, Texas Instruments Inc., Santa Clara (CA), USA

This paper discusses the losses analysis of low power high-frequency Wireless Power Transfer Systems (WPTSs). The global influence of semiconductor devices parameters on the overall WPTS perfromances is numerically discussed herein. Experimental measurements on a 2W@6.78MHz WPTS for wearable applications demonstrate the validity of the analysis.

15:00-15:20

A 3.6μW, 0.65V Regulator with an Embedded Temperature Compensated Voltage Reference

Fu-To Lin, Jui-Hsiang Tsai and Yu-Te Liao

This paper presents a 0.65-V flipped voltage follower (FVF)-based regulator with an embedded sub-1-V voltage reference. A low-pass filter is employed in the current coupling path to reduce the bias noise and improve the power supply rejection (PSR) at a low-frequency band (<kHz). The chip is fabricated in a 0.18-μm CMOS process and occupies an active area of 0.076 mm2. The proposed FVF regulator achieves a temperature coefficient of 68-ppm/°C over 0-100 °C, with a PSR of -50 dB at 1 kHz, and can drive a 0-3 mA load current while consuming only a quiescent current of 4.5 μA at a 0.8 V supply.

15:20-15:40

A MATLAB Graphical User Interface for Battery Design and Simulation; From Cell Test Data to Real-World Automotive Simulation

Abbas Fotouhi1, Neda Shateri1, Daniel J. Auger1, Stefano Longo1, Karsten Propp1, Rajlakshmi Purkayastha2 and Mark Wild2

1Advanced Vehicle Engineering Centre, SATM, Cranfield University, MK43 0AL, UK; 2OXIS Energy, Culham Science Centre, Abingdon, Oxfordshire OX14 3DB, UK

This paper describes a graphical user interface (GUI) tool designed to support cell design and development of manufacturing processes for an automotive battery application. The GUI is built using the MATLAB environment and is able to load and analyze raw test data as its input. After data processing, a cell model is fitted to the experimental data using system identification techniques. The cell model’s parameters (such as open-circuit-voltage and ohmic resistance) are displayed to the user as functions of state of charge, providing a visual understanding of the cell’s characteristics. The GUI is also able to simulate the performance of a full battery pack consisting of a specified number of single cells using standard driving cycles and a generic electric vehicle model. After a simulation, the battery designer is able to see how well the vehicle would be able to follow the driving cycle using the tested cells. Although the GUI is developed for an automotive application, it could be extended to other applications as well. The GUI has been designed to be easily used by non-simulation experts (i.e. battery designers or electrochemists) and it is fully automated, only requiring the user to supply the location of raw test data.

16:00-17:40Energy Harvesting
Room 02.1
Chair: Elena Blokhina
16:00-16:20

A Multi-cell SC DC-DC Converter Controller with Power Aware Output Ripple Reduction

Ricardo Madeira, João P. Oliveira, and Nuno Paulino

Departamento de Engenharia Electrotécnica, Faculdade de Ciências e Tecnologias da Universidade Nova de Lisboa, UNINOVA - Centre of Technology and Systems (CTS)

This paper describes a method for reducing the output voltage ripple of a SC DC-DC converter. In a SC converter the clock frequency is proportional to the output power, meaning that for low power levels the resulting low frequency value translates into a large output voltage ripple. Since the clock frequency is inversely proportional to the flying capacitance value, it is possible to reduce the output voltage ripple by decreasing the flying capacitance when the output power is small. An asynchronous controller, uses the clock period to add or subtract capacitors (multi-cell) to the flying capacitance, maintaining a low ripple voltage. Simulation results show that this technique reduces the output voltage ripple by 6.2 times in the worst case, when compared to a single-cell converter, without any significant decrease in the overall efficiency.

16:20-16:40

Determining the Optimum Power of an Electrostatic Kinetic Energy Harvester with Parasitic Capacitances

Sean Judge1, Eoghan O’ Riordan1, Dimitri Galayko2, Philippe Basset3 and Elena Blokhina1

1University College Dublin; 2Universitie Pierre et Marie Curie - Sorbonne; 3Universitie Paris Est / ESIEE Paris

Concerning the design of electrostatic kinetic energy harvesters, it is vital to be able to extract the greatest amount of power possible as the quantities obtained are typically quite small in comparison to other more developed power source technologies. In this article, we investigate the effects on the power generated of three of the more significant control parameters. These include the load resistance, the bias voltage and the external vibrating frequency of the surroundings that the device will be subject to. At first, we will look at the behaviour of the power generated with the inclusion of different forms of parasitic capacitances and then compare these results to an experimental device. Finally, we will proceed to calculate the optimum power produced over a range of possible external frequencies and these results will then be used as a model to the experimental devices.

16:40-17:00

Piezoelectric energy harvesting system for hostile environments

G. Pangallo, S. Rao, R. Carotenuto, F.G. Della Corte

Department of Information Engineering, Infrastructures and Sustainable Energy, DIIES, Università degli studi "Mediterranea" Reggio Calabria 89122, Italy

An energy harvester operating at high temperature, up to T=300 °C, is presented. In particular, a voltage doubling rectifier realized with two 4H-SiC Schottky diodes is used to rectify the AC voltage output of a piezoelectric bimorph with a Curie temperature of TC=320 °C. The rectifier efficiency is of about η~89% and it slightly increases with temperature due to the corresponding diodes threshold voltage decrease.

17:00-17:20

Remote Sensor Networks with Efficient Energy Harvesting Architecture

P. Di Marco, A. Leoni, L. Pantoli, V. Stornelli and G. Ferri

Department of Industrial and Information Engineering and Economics, University of L’Aquila - L’Aquila, Italy

This work presents a high dynamic range and high efficiency energy harvesting system for low power sensors architecture. The circuit has been conceived as a dual band architecture able to capture the largest amount of EM radiation available in the urban environment and to provide an autonomous device potentially with infinitive cycle of use. The device is tuned to receive both GSM and Wi-Fi frequencies and a power battery loading circuitry is available on board to guarantee the required energy for the autonomous sensor to work. The system handles an incoming power typically ranging from -20dBm to 20dBm by rectifying the variable input signals into a DC voltage source. Theoretically speaking, the rectified power is greater than 50% for an incoming power between -5dBm and 15dBm and test measurements succeeded with compliant results. As a typical applications load we considered a commercial gas sensor for Carbon Dioxide (CO2) detection. The whole system, designed using a discrete board, has been also conceived in order to be completely integrated in a standard CMOS technology.

17:20-17:40

A 4-nW Voltage Sensor with Configurable Hysteresis for RF Harvesters

Hugo Gonçalves, Fábio Rabuske, Diogo Santos and Jorge Fernandes

INESC-ID, Instituto Superior Técnico, Universidade de Lisboa, Portugal

This paper presents a very low power voltage sensor with configurable hysteresis usable for RF power circuits. The circuit is based on a low power reference voltage and comparator to trigger a control signal when a specific voltage is reached. The voltage trip points are configurable through the use of external resistors. To counter temperature and process variations a compensation circuit is developed. The proposed prototype circuit comprises a power enable, a backup charge and a voltage limiter designed in a standard 130-nm CMOS technology. The complete hysteresis voltage sensor exhibits a very low power consumption of only 4 nW. The simulation results exceed the performance of previously reported voltage sensors in standard analog CMOS technology.

16:00-17:40 Memristors
Room 02.2
Chair: Engin Afacan
16:00-16:20

Emulating the Physical Properties of HP Memristor Using an Arduino and a Digital Potentiometer

Olufemi A. Olumodeji1,2 and Massimo Gottardi2

1Centre for Materials and Microsystems, Fondazione Bruno Kessler, Via Sommarive, 18, 38123-Trento, Italy; 22Department of Industrial Engineering, University of Trento, Via Sommarive, 9, 38123-Trento, Italy

This paper describes a memristor emulator made up of an arduino-controlled digital potentiometer (DigPot) implementing the mathematical equations governing the HP memristor model. The emulator composed of off-the-shelf electronic components come in handy at a time where reliable physical devices are yet to be available. The arduino samples the voltage difference between the two terminals of the DigPot’s resistance network, calculates the resistance and then updates the DigPot through the SPI interface. Data is collected through the serial port and plotted in real time. This hobbyist-style do-it-yourself approach can be used to initiate students into the basic theory of memristors.

16:20-16:40

Towards Robust Implementation of Memristor Crossbar Logic Circuits

Lei Xie

Delft University of Technology, Delft, the Netherlands

Memristor crossbar is a promising technology for future VLSI circuits due to its scalability, non-volatility, high integration density, etc. However, sneak path currents in the crossbar pose major robustness challenges. One proposed solution is applying half-select voltages to floating nanowires (which are not involved in logic operations). This paper analyzes the sneak path issue after applying half-select voltages, and then uses this analysis to derive a set of realization parameter constraints for robustness. In addition, the constraints are used to estimate maximal crossbar size of logic circuits. As a case study, a one-bit full adder is implemented and verified with SPICE simulations; the results show that the proposed approach accurately predicts the impact of sneak path currents with a maximal error of 0.06V.

16:40-17:00

Effect of Hf Metal Layer on the Switching Characteristics of HfOx-based Resistive Random Access Memory

Behnoush Attarimashalkoubeh1, Jury Sandrini1, Elmira Shahrabi1, Marios Barlas2 and Yusuf Leblebici1

1Microelectronic Systems Laboratory EPFL Lausanne, Switzerland; 2Advanced Memory Group CEA-LETI Grenoble, France

In this study, we propose the insertion of an ultrathin Hf layer at the interface between TiN (top electrode) and HfOX (electrolyte), and then studied its effect on the device electrical properties. In order to obtain the desired switching characteristics, the Hf layer thickness must be precisely engineered. The device with optimized Hf layer thickness exhibits better uniformity and lower forming voltage. This could be explained by the role of Hf layer in the creation of permanent oxygen vacancies in the oxide layer, which facilitates the switching phenomena.

17:00-17:20

Hybrid Threshold-Boolean Logic Mapped on Memristor Crossbar

Lei Xie

Delft University of Technology, Delft, the Netherlands

Novel technologies are under research for future VLSI circuits. Memristor is a promising candidate due to its scalability, non-volatility, etc. This paper proposes novel implementations of threshold gates which can be mapped on memristor crossbar. Then, a new methodology is proposed to design logic circuits using both threshold and Boolean gates. To explore the scalability of the methodology, two 32-bit adders (using two different one-bit full adders as basic units) are designed as a case study. Both 32-bit adders can work in sequential or pipeline mode. The proposed two 32-bit adders are verified by SPICE simulations. The full adder outperforms the-state-of-art in terms of area (up to 58.5% decrease) and dynamic energy consumption (up to 64% decrease) with a slight penalty in delay (1 or 3 cycles). In addition, 32-bit adders require less area (up to 59%).

17:20-17:40

An aVLSI driving circuit for memristor-based STDP

Simone Acciarito, Alessandro Cristini, Luca Di Nunzio, Gaurav Mani Khanal, Gianluca Susi

Department of Electronics Engineering, University of Rome "Tor Vergata", Rome, 00133 IT

The main goal in realizing aVLSI (analog VLSI) systems able to mimic functionalities of biological neural networks is pointed to the reproduction of realistic synapses. Indeed, because of the relative high synapse/neuron ratio, especially in the case of extremely dense networks (i.e., reproduction of a real scenario), synapses represent a considerable limitation in terms of waste of silicon area and power consumption as well. Thanks to advancement made in the implementation of memristor, the interest in bio-inspired neural network design has been renewed. Memristors have tunable resistance which depends on its past state; this is analogous to the operating mode of biological synapses. In this paper, we present the circuit implementation of a simple memristor-based neural network. Here, we propose a driving circuit model that not requires specific shape input pulses to change the memristor conductance (i.e., synaptic strength), but it can be driven by arbitrary shaped input pulses. Moreover, this prototype circuit offers the chance of emulating the standard STDP behavior allowing "controlled" changes for the synaptic weights. Some preliminary experimental results are reported to validate the proposed driving circuit.

16:00-17:20 Emerging Technologies and Applications I
Room 02.3
Chair: Ricardo Póvoa
16:00-16:20

Systematical study of traps in AlN/GaN/AlGaN HEMTs on SiC Substrate by Numerical TCAD Simulation

N. K. Subramani, A. K. Sahoo, J-C. Nallatamby, R. Sommet, R. Quéré

University of Limoges, CNRS, XLIM UMR7252, F-19100, Brive, France

In this work, we investigate the impact of GaN channel traps on the performance of AlN/GaN/AlGaN HEMT device grown on SiC substrate using two-dimensional TCAD physics based simulations. Traps specifications used here are acquired from the data reported in the literature. The simulated DC characteristics are compared with experimental measurements for validation, providing an appropriate feedback for future technological improvements. Furthermore using the Low Frequency (LF) AC simulations results, we demonstrate that the LF admittance dispersion measurement is an effective tool for identifying the traps in the device structure.

16:20-16:40

Using Ion/Ioff to Predict Switch-Based Circuit Accuracy in an Extended Temperature Range up to 300°C

Jonas Tallhage1, Holger Kappert1 and Rainer Kokozinski2

1Fraunhofer Institute for Microelectronic Circuits and Systems IMS, Finkenstr. 61, 47057 Duisburg, Germany; 2University Duisburg-Essen, Department of Electronic Components and Circuits, Bismarckstr. 81, 47057 Duisburg, Germany

In a top-down design approach sensible decisions about system architecture are hard to make unless one can obtain reasonable predictions about the performance of building blocks such as ADCs or amplifiers. When an extended temperature range up to 300°C is targeted the problem is exacerbated by the large variations in device characteristics over temperature. A fundamental choice to be made is if and where to employ discrete-time (DT) rather than continuous-time (CT) techniques. In making this choice it must be considered whether transistor switches can be implemented well enough to allow the desired precision to be achieved. The Ion=Ioff figure of merit provides a good measure of the quality of transistor switches, in this paper derivations are made which map this figure of merit to a rough prediction about the precision achievable using DT circuitry. It is found that such techniques face significant problems at high temperatures, some possible block-level architectural techniques are suggested which may be able to expand the temperature range in which DT approaches are applicable.

16:40-17:00

A Chip-Level Post-CMOS Via-Last Cu TSV Process for Multi-Layer Homogeneous 3D Integration

Seniz E. Kucuk Eroglu1, Woo Yeong Cho2 and Yusuf Leblebici1

1Ecole Polytechnique Federal de Lausanne (EPFL), Lausanne, Switzerland; 2Samsung Electronics, Seoul, Korea

In this paper, a die-level CMOS post-processing scheme for 3D integration using the via-last approach is presented for multi-layer stacking. The process includes TSV fabrication, chip-to-chip bonding, and finally the TSV filling with Cu electroplating. The proposed process flow is used to fabricate a 4-layer chip stack using homogeneous CMOS memory chips. Electrical measurements are carried out to determine the resistance value of the TSVs. Kelvin bridge method is used in order to eliminate the additional resistance introduced by the experimental setup, and the average resistance value of a single TSV is determined as 180 mΩ. The current carrying capability is also investigated for possible electrical failures. It is concluded that the TSVs can carry up to 1.5 A (DC) current values without any failure.

17:00-17:20

Temperature sensitivity analysis of polarity controlled electrically doped Hetero-TFET

Kaushal Nigam, Sunil Pandey, P. N. Kondekar and Dheeraj Sharma

ECE Dept., PDPM Indian Institute of Information Technology, Design and Manufacturing Jabalpur, India

Polarity controlled (GaAs-Ge) hetero-TFET based on the concept of electrically doped mechanism have shown significant advantages in terms of high Ion current, less ambipolar leakage, less short-channel effects (SCEs) over Si-TFET. However, temperature sensitivity analysis of such a device were not analysed. Therefore, in this work, sensitivity towards temperature variation of recently proposed polarity controlled (GaAs-Ge) hetero tunnel field-effect transistor (H-TFET) is reported. The analog/RF figure-of-merits were considered to analyse the temperature sensitivity analysis of recently reported polarity controlled H-TFET. The simulations were performed using ATLAS technology computer aided design (TCAD) device simulator. We analysed that the Ion/Ioff current of polarity controlled H-TFET decreases with temperature, while, Ioff increases with temperature because of different scattering mechanisms at higher temperature. The variation in gm is 0.2mS for 0.1V gate voltage variation at different temperature in the saturation region. With a small variation in analog/RF FOMs with temperature, we can say that the proposed H-TFET is less sensitive towards temperature variation and can be used for high temperature applications.

16:00-18:00EDA Competition I
Auditório
Chair: Rafael Castro-Lopez
16:00-16:30

Evaluation of Genetic Algorithms, Particle Swarm Optimisation, and Firefly Algorithms in Antenna Design

H.J. Mohammed1,2, F. Abdulsalam2, A.S. Abdulla1, R.S. Ali1, R.A. Abd-Alhameed2, J.M.Noras2Y.I. Abdulraheem1,2, A. Ali2, J. Rodriguez2,3 and Abdelgader M. Abdalla3

1Dept. of Electrical Engineering, University of Basrah, Iraq; 2School of Electrical Engineering and Computer Science, University of Bradford, UK; 3Instituto de Telecomunicações - Aveiro, 3810-193 Portugal

Evolutionary optimization techniques with multiple objectives are applied to the design of microstrip antennas. The biologically inspired algorithms, Particle Swarm Optimization, Genetic Algorithms and the Firefly Algorithm, are integrated in new software, Antenna Optimizer, which combines attributes of the electromagnetic design environment of CST Microwave Studio with those of the technical computing and programming environment of MATLAB. Impedance matching and gain improvement are optimized over a predefined frequency range, resulting in a very small and compact 12 mm x 21 mm ultra-wideband antenna which was fabricated and measured.

16:30-17:00

Reliable Design Methodology: The Combined Effect of Radiation, Variability and Temperature

Fernando García-Redondo, Marisa López-Vallejo, Hernan Aparicio and Pablo Ituero

Department of Electronic Engineering, Technical University of Madrid, UPM

The effects caused by variability, temperature, radiation or aging may compromise the reliability of electronic circuits. Circuits designers must consider their combined effects early during the design cycle, even though it is a time and effort demanding task. In this work we present a methodology and simulation framework for the reliable design of circuits working under realistic conditions such as a wide range of temperatures, radiation and process variations. This proposal provides an alternative method for validating digital and analog circuits. Depending on the analyzed circuit functionality, the user is able to define complex reliability metrics such as signal upsets, delays or frequency deviations to measure the circuit response in affordable simulation time.

17:00-17:30

Safety-oriented Mixed-Signal Verification of Automotive Power Devices in a UVM Environment

Sebastian Simon1, Özlem Karaca1, Jérôme Kirscher1, Alexander Rath1, Georg Pelz1 and Linus Maurer2

1Infineon Technologies AG; 2Bundeswehr University Munich

The complexity of automotive applications is continuously increasing, leading to a growing demand for methodologies that offer comprehensive mixed-signal verification. However, compared to the highly automated verification methodologies in the digital domain, pre-silicon verification in the analog domain still implies a substantial amount of manual work and computational effort. Apart from this, automotive applications most often have to comply with functional safety standards and therefore their robustness concerning safety-critical faults needs to be proven. This is normally ensured by performing safety verification with faults being purposefully injected into the designs. In this paper we present a methodology that enables a regression-based mixed-signal verification combined with an existing approach for analog safety analysis. Both concepts are applied to an automotive design, in which faults have been injected, in order to demonstrate their capabilities.

17:30-18:00

Yield Optimization using K-Means Clustering Algorithm to reduce Monte Carlo Simulations

António Canelas, Ricardo Martins, Ricardo Póvoa, Nuno Lourenço and Nuno Horta

Instituto de Telecomunicações/Instituto Superior Técnico - ULisbon, Lisboa, Portugal

This paper presents an efficient yield optimization approach using k-means clustering algorithm to reduce Monte Carlo (MC) simulations. This approach uses a commercial electrical simulator and PDK models for evaluation purposes. The method was integrated in an analog IC design flow that includes the AIDA-C circuit sizing optimization tool. The proposed yield estimation technique reduces the number of required MC simulations during the optimization process. The simulated solutions are the most likely to populate the Pareto optimal front and result from a selection process based on a modified k-means algorithm. The proposed approach leads 75% reduction in the total number of the MC simulations for the presented case study.

WEDNESDAY, June 29th
10:20-12:00Data Converters II
Room 02.1
Chair: João Goes
10:20-10:40

A Study on Op-amp Nonlinearity in a Single-bit CT ΔΣ Modulator Employing GBW Compensation

Chao Chu, Johannes Wagner, Ahmad Al Marashli, Jiazuo Chi, and Maurits Ortmanns

Institute of Microelectronics, University of Ulm, Ulm, Germany

This work investigates the nonlinear effect of the 1st operational amplifier (op-amp) in a CT ΔΣ modulator with finite gain-bandwidth product (GBW) compensation. A behavioral opamp model employing a hyperbolic tangent expression has been created and verified to approximate the op-amp nonlinear characteristics. In analyzing transient simulations of ΔΣ modulators compensated for different GBWs, the influence of the 1st opamp nonlinearity has been studied, indicating that more stringent linearity requirement on the 1st op-amp must be satisfied in the modulator compensated for lower GBW. This issue can be addressed by increasing the op-amp DC gain, or by employing a mixed feedforward/feedback (FF/FB) architecture, which outperforms the cascade of integrators with feedback (CIFB) topology concerning linearity due to the reduced internal swing, thus allowing both GBW compensation and relaxed linearity requirements.

10:40-11:00

STF Engineering in CT Sigma-Delta Modulators using www.sigma-delta.de

Johannes Wagner, Rudolf Ritter and Maurits Ortmanns

Institute of Microelectronics, University of Ulm, D-89081 Ulm, Germany

This paper presents a straightforward method of STF engineering in continuous-time ΣΔ modulators within the web-based design tool www.sigma-delta.de. There are already different well known methods to obtain the STF depending on constraints given by the designer. One possibility is the analytical derivation of the high-level coefficients yielding a certain STF. Further, the ΣΔ modulator can be embedded into a filter with the desired characteristic or vice versa. However, as the NTF and STF are dependent upon each other, they cannot be chosen independently. The web-based design tool for continuous-time ΣΔ modulators relies on a heuristic search based on a genetic algorithm that is able to determine a STF complying to given constraints while maximizing the signal-to-noise ratio of the chosen modulator architecture at the same time. This paper shows the capabilities of the publicly available design tool in regard of STF engineering and gives corresponding examples.

11:00-11:20

Multichannel Time Interleaved ADC for Sensor Interfaces

MohammadReza Baghbanmanesh, Franco Maloberti

Department of Electrical, Computer, and Biomedical Engineering, University of Pavia, Pavia, Italy

A possible architecture of time-interleaved Incremental extended-range ADC (TIADC) is presented. In this paper, the operation of proposed TIADC including a SAR as extended range A/D is described. The limits finite op-amp gain and mismatch between the time-interleaved channels is analyzed. A solution that limits the effect of mismatch to small gain errors in each channel is discussed. Simulation results provide design direction for obtaining high-resolutions ADC converters. The use of op-amp with more than 90 dB gain allows achieving resolutions in the 14 bit range or more.

11:20-11:40

A 10 bit A-to-D converter development within power optimized BCD technology

Antonio D'Amico1,2,3, Florian Brugger2, Dieter Härle3, Luca Petruzzi2, Andrea Baschirotto1

1Dep. Of Physics, University of Milano-Bicocca, Milan, Italy, 2Infineon Technology, Villach, Austria, 3KAI, Villach, Austria

This paper presents the development of a 10b ADC dedicated to the digitalization of a sensing current within advanced automotive applications. The presented ADC has been developed in a power optimized BCD technology, i.e. a process specifically optimized for power delivery and featuring signal processing capabilities. However it presents some limitations, i.e. highly non-linear capacitances, large mismatch, etc.. In this scenario a 10b ADC has been developed by means of a customized MATLAB model enabling the target performance achievements. The aim of this work is to study the effect of nonideal components on the conversion performances focusing in particular on the technology limitations, like capacitors nonlinearity and components mismatch. In order to achieve this, a Matlab model has been developed and then a demonstrator circuit has been designed at transistor level.

11:40-12:00

A 2.3mW Quadrature Bandpass Continuous-Time ΔΣ Modulator with Reconfigurable Quantizer

Tobias Saalfeld, Aytac Atac, Lei Liao, Ralf Wunderlich, Stefan Heinen

Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany

This paper presents a continuous-time (CT) quadrature bandpass (QBP) ΔΣ ADC which is reconfigurable in terms of quantizer resolution, bandwidth (BW) and IF. It is designed for use in a low power low-IF multi-band transceiver system. In simulations the presented implementation in a 130nm RF CMOS process achieves a resolution of 10.5 bit. Additionally, a total power consumption of 2.3mW from an 1.2V supply voltage is simulated. The BW of the 3rd order QBP filter can be set to 0.5, 1.0 or 2.0MHz together with the IF. Likewise the loop quantizer is capable of single and dual-bit analog to digital conversion. Separate digital to analog converters (DAC) for both modes are used in the feedback of the ΔΣ loop. Furthermore an improved data weighted averaging (DWA) algorithm is presented to control the dual-bit DAC unity cells and cope with the DACs I/Q mismatch.

10:20-12:00Power ICs I
Room 02.2
Chair: Alberto Gola
10:20-10:40

A Mode-of-Operation Based Switching Technique for SIDO Buck-Boost Converter

Arunkumar Salimath, Edoardo Bonizzoni, Franco Maloberti

Department of Electrical, Computer and Biomedical Engineering, University of Pavia, Pavia, Italy

This article presents a switching technique for the Single Inductor Double Output (SIDO) buck-boost converter. The proposed switching technique improves the overall efficiency of the SIDO DC-DC converter by (i) automatically differentiating between buck and boost dominated modes of operation and (ii) providing a need-based charging phase to the system only in the boost-dominated load conditions. In addition, using the proposed technique, the outputs are regulated efficiently across the input/line variations. The generation of switching phases is entirely by error processing and simplified. System level simulation of the SIDO buck-boost converter is performed and the relevant results are provided.

10:40-11:00

A chopper stabilized, low power capacitance to PWM converter for sensor interfacing

S. Del Cesta1, L. Intaschi1, P. Bruschi1, M. Piotto2

1Dipartimento di Ingegneria dell'Informazione, University of Pisa, Pisa, Italy, 2IEIIT - Pisa, CNR, Pisa, Italy

A low-power, low voltage capacitance to pulse duration converter with intrinsic low sensitivity to temperature and parasitic capacitances is presented. The circuit uses a dual clock chopper modulation, which significantly lowers the effects of device mismatch. An effective resolution of 7.2 bits with 3.8 uA supply current and operation down to 0.9 Vdd are demonstrated by means of electrical simulations performed on a prototype designed with the UMC 0.18 um process.

11:00-11:20

Boost Converter with Load Dependent Adaptive Controller for Improved Transient Response

Samuel Quenzer-Hohmuth1, Steffen Ritzmanny2, Thoralf Rosahly2 and Bernhard Wicht1

1Robert Bosch Center for Power Electronics, Reutlingen University, Reutlingen, Germany, 2Robert Bosch GmbH, Reutlingen, Germany

Size and cost of a boost converter can be minimized by reducing the voltage overshoot and fastening the transient response in case of load transient. The presented technique improves the transient response of a current mode controlled boost converter, which usually suffers from bandwidth limitation because of its right-half-plane zero (RHPZ). The proposed technique comprises a load current estimation which works as part of a digital controller without any additional measurements. Based on the latest load estimation the controller parameters are adapted, achieving small voltage overshoot and fast transient response. The presented technique was implemented in a digital control circuit, consisting of an ASIC in a 110 nm-technology, a Xilinx Spartan-6 field programmable gate array (FPGA), and a TI-ADS8422 analog-to-digital-converter (ADC). Simulation and measurements of a 4V-to-6.3V, 500mA boost converter show an improvement of 50% in voltage overshoot and response time to load transient.

11:20-11:40

Comparing Composite vs. Wave-Cores in a Novel Dark-Silicon Methodology

Antonio Arnone, Chris Bailey

Department of Computer Science, University of York, York, United Kingdom

As transistor scaling continues to push us into new design spaces, where power density is increasingly a major performance constraint, there have been moves to explore solutions which exploit so-called Dark Silicon, the UCSD Greendroid project being a notable exemplar. In this paper, we explore one novel dark silicon methodology, based on a heterogeneous multi-accelerator system model and an implicit execution model for the host processor. We also highlight a backend translation methodology from raw machine code into dataflow style hardware cores, and introduce two distinct implementation styles. We then demonstrate comparative power benefits as compared to a relevant CPU model, assuming a 65nm benchmark technology node for both cases.

11:40-12:00

Simulation and development of high precision voltage dividers and buffer for AC voltage metrology up to 1 MHz

Bjørnar Karlsen1,2, Kåre Lind1, Helge Malmbekk1 and Per Ohlckers2

1Justervesenet, 2HSN, University College of Southeast Norway

A voltage divider and buffer system has been proposed in order to improve the AC Voltage traceability at Justervesenet (JV) for frequencies up to 1 MHz. Buffer prototypes have been constructed for use at room temperature and liquid nitrogen. They have proven ability to operate up to 1 MHz with a 50 Ω load at 300 K and beyond 10 MHz for loads above 1 kΩ. Simulations suggest that AC-DC difference span less than 30 ppm for frequencies up to 1 MHz for the divider and 200 ppm for the buffer. Although there are some discrepancies between buffer simulation and prototype measurements, the model still possess great explanatory power.

10:20-12:00Modeling & Layout Techniques II
Room 02.3
Chair: Jürgen Scheible
10:20-10:40

An Optimization-Based Design Methodology with PVT Analysis for Ultra-Low Voltage Analog ICs

Lucas C Severo1,2 and Wilhelmus A. M. V. Noije2

Federal University of Pampa, University of São Paulo, Brazil

This paper presents a design methodology for ultra-low voltage (ULV) analog integrated circuits. This methodology is based on an optimization process using Simulated Annealing (SA) heuristic and electrical simulations. The SA algorithm explores the design space to obtain design feasible solutions at the same time that the effects of process, voltage and temperature (PVT) variations are analyzed with corners simulations. Using the proposed methodology, a 0.6 V low-pass filter is designed in two steps, as a bottom-up approach. The results show a designed 0.6 V active filter with 2.47 MHz cut-off frequency and power dissipation of 640 μW, in according with the IEEE 802.15.4 standard for 2.5 GHz low power receivers.

10:40-11:00

A Comprehensive Verilog-A Behavioral Model of Spin-Transfer Torque Memory Cell

Yilkal A. Belay, A. Cabrini, G. Torelli

Department of Electronics, University of Pavia. Pavia, Italy

Spin-Transfer Torque RAM (STT-RAM) has emerged as a potential candidate for universal memory. An electrical model of STT-RAM cell is needed to adequately explore the design space of the device. In this paper, a comprehensive and compact Verilog-A behavioral model of STT-RAM cell is presented. The model captures both dynamic switching aspects and static properties of the magnetic tunnel junction (MTJ), which is the basic storage device in the STT-RAM cell. The dynamic switching behavior is modeled using Bernoulli random binary number generator in combination with switching probability function. The static behavior was represented by means of a variable resistor with bias current/voltage dependent lowand high- resistance values. In addition to its compactness and comprehensiveness, the model is suited to be used within standard integrated circuit CAD tools for analog and mixed-signal design simulation.

11:00-11:20

An Efficient Model for Evaluating Current in Silicon Nanocrystals

M.A. Mehdy, A. Antidormi, M. Graziano, G. Piccinini

Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy

In this paper we present an efficient model for current calculation through silicon nanocrystals. The model uses self consistent field approach to calculate the evolution of transmission spectra and Landauer formalism for current calculations. We implemented the split in spectra for different spin so that the model works in case of coulomb blockade. A few simulations were performed using a physical simulator to extract parameters to be inserted in model. The current voltage characteristics were calculated from the model for structures with different geometry and coupling strength between the lattice and contacts. The results from the model show good accordance with those from physical simulator and are obtained with more than two orders of magnitude speed up.

11:20-11:40

Calculation of Very Near Field Radiated Emission of a Straight Cable Harness

Herbert Hackl1, Bernhard Auinger

1NXP Semiconductors Austria, Gratkorn, Austria, 2Institute of Electronics, Graz University of Technology, Graz, Austria

Radiated emissions generated by an integrated circuit (IC) during operation must not exceed specific limits. For automotive ICs this is verified by the standardized ALSE (Absorber Lined Shielded Enclosure) measurement setup defined in the CISPR 25 standard. This test especially targets the Efield emitted by a long cable harness attached to the device under test. Apart from simulations, analytical calculation models can be applied to quickly estimate the compliance test results. Typically the Hertzian dipole antenna model is used to calculate the electric field radiating from cables. But during the ALSE test radiated emissions from 150 kHz to 1GHz are measured in 1m distance. This results in very near field conditions for the lower frequencies, where the common prediction model is at its theoretical limits. As an alternative this paper demonstrates an electrostatic approach. For the frequency range of 100 kHz to 30MHz constant transmission factors are derived which yield the radiated emission spectrum when applied to the IC’s output signal spectrum. The results of both calculation models are compared to measurement data.

11:40-12:00

gPCDS: An Interactive Tool for Creating Schematic Module Generators in Analog IC Design

Matthias Greif, Daniel Marolt, Juergen Scheible

Robert Bosch Center for Power Electronics, Reutlingen University, Germany

Optimization-based design automation for analog ICs still remains behind the demands. A promising alternative is given by procedural approaches such as parameterized generators, also known as PCells. We are working on a complete analog design flow based on parameterized generators for entire circuits and corresponding layout modules. Because the conventional programming of such enhanced generators is far too complicated and costly, new methods are needed to ease their development. This paper presents gPCDS (graphical PCDS), a novel tool for a designer-oriented development of schematic module generators, integrated into a common schematic entry environment. The tool is based on PCDS (Parameterized Circuit Description Scheme), a meta-language for the creation of parametrized analog circuits. Schematic module generators are a very desirable complement to layout module generators in order to achieve a seamless schematic- driven layout design flow on module level. By facilitating a way of generator development that matches a design expert’s mentality, gPCDS contributes to close this gap in the analog design flow.

10:20-12:00Fault Simulation and Reliability
Auditório
Chair: Francisco V. Fernandez
10:20-10:40

Efficient Signature Selection Tool for Sense & React Systems

Engin Afacan1, Günhan Dündar1, Ali E. Pusane1, Faik Baskaya1, and Mustafa B. Yelten2

1Department of Electrical and Electronics Engineering, Bogazici University, 2Department of Electrical and Electronics Engineering, Istanbul Technical University

Reconfigurable circuit design has become very important in the last decade for increasing the lifetime of CMOS circuits in deep sub-micron technologies. Sense & React approach is one of the reconfigurable design approaches, where degradation in a circuit performance is detected via sensor circuitry and a pre-established recovery operation is applied to circuit. However, sense operations are quite problematic since direct measurement of the degradation in circuit performance is highly complicated. Therefore, indirect measurements are preferred, in which one or more relevant circuit variables, which are called signatures, are selected out of measurable circuit quantities. Conventionally, the designer selects the signatures by performing an iterative search and evaluation on aging simulation results, and no such procedure has been defined in the literature yet. This paper proposes an efficient selection methodology and tool for determining efficient signatures for sense operation.

10:40-11:00

Finite Difference Method for Electromigration Analysis of Multi-Branch Interconnects

Chase Cook1, Zeyu Sun1, Taeyoung Kim2, Sheldon X.-D. Tan1

1Department of Electrical and Computer Engineering, University of California, Riverside, CA 92521, 2Department of Computer Science and Engineering, University of California, Riverside, CA 92521

Electromigration (EM) in VLSI chips has become a major reliability issues in nanometer VLSI design. Traditional compact EM models cannot give accurate predictions about the stress evolution over all stress conditions for complicated multi-branch interconnect structures. In this paper, we try to mitigate this problem by performing finite difference method (FDM) for the EM effects in multi-branch interconnects based on the kinetics of the first principle of EM physics. We start with the partial differential equations that describe the fundamental hydrostatic stress evolution for both the void nucleation and void growth phases with proper boundary and initial conditions for typical multi-branch metal wires: the single 2-terminal wire, and the straight-line 3-terminal wires. The new FDM for EM analysis approach can easily accommodate existing nonuniformly distributed residual stress, while existing compact EM models cannot. Time varying temperature and current, which are also difficult to model with existing methods, can also be considered with this method. Numerical results show that the proposed FDM EM analysis method agrees with the COMSOL based finite element method in terms of accuracy.

11:00-11:20

Fault Grouping for Fault Injection Based Simulation of AMS Circuits in the Context of Functional Safety

Oezlem Karaca1, Jerome Kirscher2, Arnaud Laroche3, Andreas Tributsch3, Linus Maurer1 and Georg Pelz2

1Bundeswehr University Munich, Neubiberg, Germany, 2Infineon Technologies AG, Neubiberg, Germany, 3Infineon Technologies AG, Villach, Austria

The fault injection technique is utilized for simulation-based verification of safety-related analog and mixedsignal (AMS) circuits for compliance with safety requirements in the presence of hardware faults. Exhaustive fault simulation is very time consuming with respect to the number of faults to simulate at circuit level. For efficient simulation-based verification, a fault grouping approach is proposed to reduce the number of faults to simulate without missing out potentially safety-critical faults. The fault grouping approach is based on componentlevel fault simulation, hierarchical clustering and internal cluster validation. The effectiveness is investigated on a component extracted from an automotive safety-related System on a Chip.

11:20-11:40

Test structures for residual stress monitoring in the integrated CMOS-MEMS process development

Carlos Ramón Báez Alvarez, Mónico Linares Aranda, Alfonso Torres Jacome, Wilfrido Calleja Arriaga

Laboratorio de Innovación en Sistemas Micro Electro Mecánicos (LI-MEMS), Instituto Nacional de Astrofísica, Puebla México

The design of a set of test structures required to monitoring the residual stress and residual stress gradient in the development of a fabrication process that merges electronic and mechanical devices is presented. The microstructures designed have the advantage to be functional with different structural materials like polysilicon, aluminum and titanium. Beam theories have been used to obtain a wide range strain monitoring ranging from 5 MPa until more than 50 MPa. The designed test structures were validated by a finite element analysis.

11:40-12:00

Semi-Empirical Aging Model Development Via Accelerated Aging Test

Engin Afacan, Günhan Dündar, Ali E. Pusane, and Faik Baskaya

Department of Electrical and Electronics Engineering, Bogazici University

Modelling of the degradation mechanisms has a crucial role during the aging analysis, which determines the accuracy of the lifetime estimation. Conventionally, analytical and semi-empirical models are utilized during the aging analysis. Analytical models employ deterministic equations during the degradation calculation and they can be scaled for different technology nodes; hence providing flexibility. However, scaling errors and approximations during the model development may degrade the accuracy. On the other hand, semi-empirical models are generated via accelerated aging test (AAT) performed on the silicon, which often promise more reliable results for a given technology. This paper comprehensively examines the semi-empirical modelling process from test chip design to AAT experiments.

13:20-15:00IC Design II
Room 02.1
Chair: Bernd Deutschmann
13:20-13:40

Thermal Issues in Deep Sub-Micron FDSOI Circuits

Can Baltacý, Yusuf Leblebici

Microelectronic Systems Laboratory, école Polytechnique Fédérale de Lausanne

Self-heating effects became more prominent with the introduction of the modern devices like FDSOI and low thermal conductivity materials such as SiO2. Consequently, the design of high speed digital circuits which are the timecritical blocks of high performance processors started to be limited mainly by thermal issues. For observing the thermal behaviour of FDSOI structure on circuit level, a 64-bit Kogge- Stone parallel prefix adder is designed and implemented in 40nm bulk CMOS technology and thermal model of the circuit is extracted and simulated according to FDSOI design parameters. The implemented adder circuit has a critical path delay of 148ps under 900 mV power supply voltage with a power consumption of 12mW. The temperature profile of the designed circuit is extracted with thermal simulations and the peak temperature locations are examined in detail. The hot spot locations and their temperature values are correlated with the power density. It is shown that self-heating of high power density devices has a significant influence on the peak temperature of a design. Finally, a simple design solution is proposed which can significantly decrease the peak temperature.

13:40-14:00

Effect of Integrated Polysilicon Resistors on the Linearity of Composite Circuits

Gabor Varga, Lotte Geck, Iyappan Subbiah, Moritz Schrey and Stefan Heinen

Integrated Analog Circuits and RF Systems Laboratory, RWTH Aachen University, Germany

This paper describes the linearity degradation effect in integrated circuits caused by the silicide contacts of polysilicon resistors. This secondary distorting effect starts to play a role when high system linearity is required or the primary nonlinear components like transconductances are already optimized for low distortion. Physical background is given with an emphasis on circuit design using RF pcells and the effect on the linearity figure-of-merit IIP3 of composite circuits is demonstrated. The influence on a practical highly linear broadband LNA employing Complementary Derivative Superposition for Cognitive Radios is shown and recommendations to reduce or to use the effect is presented.

14:00-14:20

Design of a 64 channels current-to-frequency converter ASIC, front-end electronics for high intensity particle beam detectors

F. Fausti1, G. Mazza2, F. Marchetto2, R. Sacchi3, R. Cirio3

1National Institute of Nuclear Physics, Turin Polytechnic Ph.D. student, Physics Department of Turin University, Turin, Italy, 2National Institute of Nuclear Physics, Turin, Italy, 3National Institute of Nuclear Physics, Physics Department of Turin University, Turin, Italy

A new wide-input dynamic range, 64-channels current-to-frequency converter ASIC has been designed and is now under characterization. This chip, nicknamed TERA09, has been realized to equip the front-end readout electronics for the new generation of beam monitor chambers for particle therapy applications. In this field, the trend in the accelerator development is moving toward compact solutions providing highintensity pulsed-beams. However, such a high intensity will saturate the present readout of the beam monitor chambers. In order to deal with the technology innovations in the particle therapy, the chip described in this work is able to cope with a higher maximum intensity while keeping high resolution by working on a six orders of magnitude conversion-linearity zone (hundreds of pA to hundreds of μA), with a gain spread in the order of 1-3% (r.m.s.), with a 200fC charge resolution.

14:20-14:40

Wide Range Resistance to Current Conversion Circuit for Resistive Gas Sensors Applications

Zeinab Hijazi1,2, Daniele Caviglia1, Maurizio Valle1, Hussein Chible2

1DITEN, COSMIC Lab, University of Genova, Genova, Italy, 2EDST-MECRL Lab, Lebanese University, Beirut, Lebanon

Due to their physical principle of operation, resistive gas sensors require very wide range interface circuit. Thus, to design the integrated read out solution, the accuracy in the converted data should be preserved. In this paper, a wide range resistance to current conversion circuit for gas sensing applications is designed. High linear current mirror in push pull configuration is implemented as well. Simulation results show that the circuit achieves a percentage error in the converted current between 0.12% and 0.25% over 7 decades for the sensor’s resistance ranging from 100Ω to 1GΩ. The current mirror achieves an absolute percentage gain factor error of 0.2% and 0.46% for PMOS and NMOS current mirrors respectively.

14:40-15:00

Precoder and Decoder for Duobinary Modulation over Equalized 50-m SI-POF

J. Aguirre, C. Sánchez-Azqueta, E. Guerrero, C. Gimeno, S. Celma

Group of Electronic Design - Aragón Institute of Engineering Research (GDE I3A), Universidad de Zaragoza, Zaragoza, Spain

This work presents a novel CMOS transceiver that enables 50-m 1-mm step-index plastic optical fiber (SI-POF) to increase transmitted data rate up to 3.125 Gbps using amplitude duobinary modulation, in addition to continuous-time equalization. For that purpose, a duobinary precoder and a duobinary decoder have been designed in a cost-effective 0.18-μAm CMOS technology fed with 1.8 V, consuming 27.9 mW in total. Additionally, a new model based on low-pass Bessel filter has been proposed to simulate the effect of the equalized channel, achieving excellent agreement with experimental data. Postlayout results validate the advantages of the proposed transceiver.

13:20-14:40RF, Microwave and mm-wave Circuits I
Room 02.2
Chair: José López-Villegas
13:20-13:40

Multi-Gb/s OOK mm-Wave Modulator ICs on 28 nm Low-Power Digital CMOS

Jan Dirk Leufker, David Fritsche, Guido Belfiore, Corrado Carta and Frank Ellinger

Department of Electrical and Computer Engineering, Chair for Circuit Design and Network Theory, Technische Universität Dresden, 01062 Dresden, Germany

This paper presents two on-off-keying millimetrewave modulator ICs working with measured data rates of up to 30 Gb/s fabricated on 28nm low-power digital CMOS. The first circuit is a switched cross-coupled oscillator with oscillation frequency of 54 GHz and measured data rates of up to 6 Gb/s. The power-up time of the oscillator is minimized by generating and introducing a pulse signal into the oscillator core enabling multi-Gb/s data rate operation. Proper power-down behaviour is achieved by shortcut the LC-tank in the off-state. The circuit consumes 10mA from a 1.2 V-source. The second circuit is a compensated modulator working with carrier frequencies of up to 60GHz and measured data rates of up to 30 Gb/s while consuming 6mA from a 1.2 V-source. Both circuits compare well with the state-of-the-art.

13:40-14:00

CMOS Transimpedance Amplifier with Controllable Gain for RF Overlay

G. Royo1, C. Sánchez-Azqueta1, C. Aldea1, S. Celma1, C. Gimeno2

1Group of Electronic Design - Aragón Institute of Engineering Research (GDE-I3A), Universidad de Zaragoza, Zaragoza, Spain, 2ICTEAM Institute, Université Catholique de Louvain, Louvain-la-Neuve, Belgium

In this paper, a fully-differential transimpedance amplifier (TIA) with controllable transimpedance for use in RF overlay downstream communication systems is presented. It consists of a shunt-shunt feedback transimpedance amplifier with transimpedance and open loop gain control. The transimpedance amplifier is intended for 47 MHz to 870 MHz subcarrier multiplexed RF signals with a 18 dBΩ transimpedance gain control range. The TIA, designed in a CMOS 180 nm technology, dissipates 27 mW from a supply voltage of 1.8 V. The inputreferred noise current is lower than 6 pA√Hz to allow an optical input power from -6 to +2 dBm.

14:00-14:20

37.8 GHz to 54.6 GHz Amplifier and DC to 29 GHz Variable Gain Amplifier in 0.13 μm SiGe BiCMOS Technology

Hebat-Allah Yehia Abdeen1, Hermann Schumacher1, Volker Zieglery2, Askold Meusling2

1Institute of Electron Devices and Circuits, Ulm University, Ulm, Germany, 2Airbus Group Innovations, Ottobrunn, Germany

A one stage single-ended input/differential output cascode amplifier operating from 37.8 to 54.6 GHz and a fully differential variable gain amplifier (VGA) based on Gilbert cell topology operating from DC to 29 GHz are presented. The circuits are implemented and fabricated using a 250 GHz fT SiGe BiCMOS technology. Both chips were characterized on-wafer. The amplifier chip shows a maximum measured gain of 13.5 dB at 44.6 GHz with an input-referred 1 dB compression point higher than -6 dBm. The amplifier chip consumes 45 mW and occupies an area of 0.23 mm2. The VGA chip exhibits a measured gain varying from -23 to 14 dB and an input-referred 1 dB compression point ranging from around -5 to +9 dBm. The VGA chip consumes 247 mW and occupies an area of 0.23 mm2.

14:20-14:40

Design of an Integrated CMOS Highly Sensitive True RMS RF Power Detector for Cognitive Radio Applications

Gabor Varga, Benedikt Wolf, Tobias van Rey, Arun Ashok, and Stefan Heinen

Integrated Analog Circuits and RF Systems Laboratory, RWTH Aachen University, 52062 Aachen, Germany

A high dynamic range true RMS power detector is designed for broadband frequency agile applications like Cognitive Radio. The RF bandwidth of the Power Detector covers 0.5 GHz - 3 GHz with a dynamic range of 50 dB and a minimum detectable power of -50dBm (50Ω). Its architecture is differential employing a pseudo-differential squaring circuit and it has a high input impedance enabling it to be placed on high impedance as well as on 50Ω lines. Particularly the noise behaviour of the circuit is investigated due to the inherently strong low-frequency noise of the squaring stage. Preamplifier stages, automatic offset cancellation, calibration and oversampling are employed to reach high sensitivity. Logarithmic amplifier stages after the squaring unit care for a linear-in-dB conversion. The power detector has been designed in a commercial UMC 130nm CMOS technology in order to provide easier integration with other mixed-signal blocks and low-cost production.

13:20-15:00Biomedical Applications II
Room 02.3
Chair: Nuno Lourenço
13:20-13:40

Towards The Integration of E-skin into Prosthetic Devices

Marta Franceschi1, Lucia Seminara1, Luigi Pinna1, Maurizio Valle1, Ali Ibrahim1,2, Strahinja Dosen3

1DITEN, COSMIC Lab, University of Genova, Genova, Italy, 2EDST, MECRL Lab, Lebanese University, Beirut, Lebanon, 3Institute of Neuro-rehabilitation System, University Medical Center Gottingen, Gottingen, Germany

Endowing appliances with the capability of sensing and processing touch enables tactile interaction between electronic devices and the environment. E-skin organized as a set of multiple sensing components and integrated with a dedicated embedded electronic system can implement the communication link between e-skin and surroundings. Basing the analysis on a relevant application example (i.e. human prosthetics), the present study describes a system including an electronic skin and a stimulation unit. The overall system was validated and tested in eight healthy subjects, who were asked to recognize the shape, position and direction of a set of dynamic mechanical stimuli presented on the electronic skin. The results demonstrated that tactile information was successfully translated from a mechanical interaction applied on the e-skin into electrotactile patterns, which the subjects could recognize with a good performance. As the obtained results are promising, in this paper the challenging requirements for the integration of e-skin into prosthetic devices were assessed, mainly focusing on computational complexity of the embedded data processing unit.

13:40-14:00

Apodization Scheme for Hardware-Efficient Beamformer

A. Ibrahim1, F. Angiolini1,2, M. Arditi2, J.-P. Thiran3, G. De Micheli1

1LSI, école Polytechnique Fédérale de Lausanne (EPFL), Switzerland, 2LTS5, école Polytechnique Fédérale de Lausanne (EPFL), Switzerland, 3Department of Radiology, University Hospital Center (CHUV) and University of Lausanne (UNIL), Switzerland

3D ultrasound is an emerging diagnostic technique that extends standard ultrasound imaging by capturing volumes, instead of planes. This brings completely new diagnostic opportunities, among which the possibility of disjoining image acquisition and analysis, thus enabling remote diagnosis, which would bring obvious medical and economic benefits. Unfortunately, 3D ultrasound is several orders of magnitude more computationally complex than 2D imaging. Therefore, algorithmic improvements to simplify the processing are mandatory in order to conceive cheap, portable, low-power imagers. The kernel of the 3D imaging process, called beamforming, consists essentially of computing delay and apodization profiles.We have previously devised an approximation of the delay calculation stage, which dramatically reduces hardware complexity. Unfortunately, this approximation introduces an intrinsic degree of inaccuracy that can be characterized as added image noise. In this paper, we identify an efficient approximated approach to the calculation of apodization profiles, that additionally minimizes (-76%) the error introduced during delay calculation. Together, these two techniques enable an efficient computation of 3D ultrasound images.

14:00-14:20

High Frequency Self-oscillating Current Switching for a Fully Integrated Fail-safe Stimulator Output Stage

Reza Ranjandish, Alexandre Schmid

Microelectronic Systems Laboratory, Swiss Federal Institute of Technology (EPFL), Switzerland

Using blocking capacitors in biomedical stimulators is important to the safety of the developed systems. However, the capacitors should be large enough in order to minimize the required voltage headroom. On the other hand, integrating large capacitors of few micro-Farads alongside the stimulator is almost impossible in implantable systems. High frequency current switching is a method that enables reducing the size of blocking capacitors. However, this method needs high-frequency square pulses, which is power consuming for the stimulators. In addition, since the frequency of high-frequency pulses is fixed, the voltage headroom required to support the blocking capacitor is not bounded. The larger the amplitude of the stimulation current, the higher the voltage headroom becomes. In this paper, an improved high-frequency current-switching method is proposed to overcome the mentioned drawbacks of the original highfrequency current-switching method. The proposed method is designed, simulated and validated using a 0.18 μm high-voltage SOI technology provided by XFAB.

14:20-14:40

A Multibias DAC for a Cortical Microelectrode Stimulator

Diogo Caetano, Jorge Fernandes and Moisés Piedade

INESC-ID Lisboa, Instituto Superior Técnico, Universidade de Lisboa, Portugal

This paper describes a digital-to-analog converter (DAC) for an intra-cortical microelectrode stimulator. The circuit is designed to generate a charge and discharge pulse, with the same amplitude, preventing charge accumulation and damage to the tissue. With 5 bits of resolution, the DAC will generate a monotonic scale with maximum amplitude of 100 μA. The DAC should be used in a large matrix of electrodes, each to be stimulated by an independent DAC. This circuit has a very low area/DAC because the bit scaling is performed in a bias circuit whereas the DAC transistors are unitary-sized transistors with a total area of 29 μm x 35 μm. There is one biphasic driver for each DAC with an area of 28.9 μm x 42,6 μm. Low area allows minimum impact to the brain and an increase in number of devices that can be used in the implant, providing greater resolution. A circuit prototype was fabricated in AMS 0.35 μm CMOS technology.

14:40-15:00

Integer-based digital processor for the estimation of phase synchronization between neural signals

James Brian Romaine, Manuel Delgado-Restituto, Juan Antonio Leñero-Bardallo and ángel Rodríguez-Vázquez

Institute of Microelectronics of Sevilla and University of Sevilla, Seville, Spain

This paper reports a low area, low power, integerbased neural digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying the specific time periods associated with two consecutive minima. The simplicity of this phase-frequency content identifier allows for the digital processor to utilize only basic digital blocks, such as registers, counters, adders and subtractors, without incorporating any complex multiplication and or division algorithms. The low area and power consumptions make the processor an extremely scalable device which would work well in closed loop neural prosthesis for the treatment of neural diseases.

13:20-15:00Heterogeneous Systems
Auditório
Chair: Ralf Sommer
13:20-13:40

Systematic MEMS ASIC Design Flow using the Example of an Acceleration Sensor

J. Klaus, R. Paris, and R. Sommer

Institut für Mikroelektronik- und Mechatronik-Systeme gemeinnützige GmbH, Ilmenau, Germany

With the help of MEMS-ASIC-development methodology the gap between a seamless design of multiphysical systems can be overcome. This contribution gives insight to MEMS2015 results of methodology for synthesis of MEMS. As an example of heterogeneous design an acceleration sensor is presented.

13:40-14:00

Hardware-Aware Performance Evaluation for the Co-Design of Image Sensors and Vision Algorithms

C. Villegas-Pachón, R. Carmona-Galán, J. Fernández-Berni and á. Rodríguez-Vázquez

Institute of Microelectronics of Seville (IMSE-CNM), CSIC-University of Seville, Spain

The top-down approach to system design allows obtaining separate specifications for each subsystem. In the case of vision systems, this means propagating system-level specifications down to particular specifications for e. g. the image sensor, the image processor, etc. This permits to adopt different design strategies for each one of them, as long as they meet their own specifications. This approach can lead to over-design, which is not always affordable. Conversely, if higher-level specifications are too tight, they can lead to impossible specifications at the lower levels. This is certainly the case for embedded vision systems in which high-performance needs to be paired with a very restricted power budget. In order to explore alternative architectures, we need tools that allow for simultaneous optimization of different blocks. However, the link between lowlevel non-idealities and high-level performance is missing. CAD tools for the design and verification of analog and mixed-signal integrated circuits are not well suited for the simulation of higher-level functionalities. Our approach is to extract relevant data from circuit-level simulation and to build an OpenCV model to be employed in the design of the algorithm. The utility of this approach is illustrated by the evaluation of the effect of columnwise and pixel-wise FPN at the sensor on the performance of Viola-Jones face detection.

14:00-14:20

A Verilog-A Model of a Charge Sensitive Amplifier for a HV-CMOS Pixel Sensor

R. Casanova and S. Grinstein

Institut de Física d'Altes Energies (IFAE), Bellaterra, Spain

The use of hybrid pixel detectors in High Energy Physics (HEP) have allowed particle tracking reconstruction with an unprecedented precision. These detectors are expensive to assembly and the bump size limits the minimum pixel size. In order to overcome those limitations full monolithic pixels are being investigated. The idea is to integrate into the same chip the sensor matrix and the readout electronics. Simultaneously, new methods for measuring the energy of the detected particles with higher precision that those achievable by using the Time Over Threshold (TOT) technique are under study. This paper presents a behavioral model of the preamplifier stage of a pixel readout channel written in Verilog-A. The purpose of this model is to allow studying different solutions for measuring the energy with higher precision without the need to design the readout channel at transistor level. The presented model is very simple and written as a function of the main parameters of the pre-amplifier stage, that is, open loop gain, bandwidth, coupling capacitor, and feedback capacitor.

14:20-14:40

Towards the simulatable specification of a highly customisable SystemC AMS alternator model in its multi-domain environment

V. Tran1,2, P. Tisserand1, F. P^echeux2, A. Pinna1

1Valeo, PES, Cr´eteil, France, 2Sorbonne Universités, UPMC Univ Paris 06, CNRS UMR 7606, Paris, France

This paper presents a refinable and customisable alternator model with its heterogeneous environment, all implemented in SystemC and SystemC-AMS. The virtual prototype can be configured easily, and the embedded software can be changed at any time. Experience has shown that the overall development time can be reduced. Indeed, with a high-level configurable description of the environment and a refinable synchronous machine system model, electronic designers can easily evaluate performances according to architecture exploration.

14:40-15:00

On the influence of angle sensor nonidealities on the torque ripple in PMSM systems - an analytical approach

Alexandra Iosub1,2, Jerome Kirscher2, Andi Buzo2, Georg Pelz2, Liviu Goras1,3

1'Gheorghe Asachi' Technical University of Iaşi, Romania, 2Infineon AG Neubiberg, Germany, 3Institute of Computer Science, Romanian Academy, Iaşi

Accurate measurement of rotor angle in Permanent Magnet Synchronous Motor (PMSM) drive applications is important when high performances as low level torque ripples are required. If the relationship between torque ripple and angle error is known, then, further steps can be done in order to reduce the level of the ripple. Based on an analytical description of the sensor model, a relationship between the angle error and speed error (seen as a noise source for the system) as well as torque ripples are deduced. Simulation results for a specific range of mechanical speed using SystemC-AMS models confirm the theoretical analysis.

15:20-17:00Amplifiers and Comparators
Room 02.1
Chair: Jorge Fernandes
15:20-15:40

Class-O power amplifier with enhanced linearity using floating body technique in 130 nm standard CMOS technology

Muhammad Abdullah Khan, and Renato Negra

High Frequency Electronics, RWTH Aachen University, 52074 Aachen, Germany

In this paper, we present a modified class-O power amplifier (PA) which employs floating-body technique to achieve high linearity. Class-O is a new PA topology which incorporates two sub-amplifiers working in parallel to achieve high linearity and efficiency. The two sub-amplifiers are operated in common drain (CD) and common source (CS) configuration. The proposed floating-body technique is verified with on-wafer measurements on single power transistors. The simulation results of overall class-O amplifier show a 2.3 dB improvement in output 1 dB compression point (Pout1dB) over the conventional body shorted to source version of the amplifier. The power added efficiency (PAE) of proposed class-O is 33.3% as compared to 24% for conventional version. Hence, enabling the proposed amplifier to transmit higher linear output power with more efficiency. The operating frequency of both the amplifiers 960MHz and the technology used is UMC 130nm standard RFCMOS.

15:40-16:00

A 55 dB Range Gain Interpolating Variable Gain Amplifier with Improved Offset Cancellation

Mohammed El-Shennawy, Niko Joram and Frank Ellinger

Circuit Design and Network Theory, Technische Universität Dresden, 01062 Dresden, Germany

This work presents the design of a 55 dB dynamic range gain interpolating variable gain amplifier (VGA). In such wide dynamic range amplifiers, small input referred offsets in the range of a few millivolts may cause the outputs to rail especially at the higher gain settings. Therefore an offset cancellation circuit is needed. The VGA design including an improved offset cancellation circuit is fabricated as part of a full automatic gain control (AGC) loop on an IBM 0.18 μm BiCMOS 7LM technology. Measurement results are in good agreement with simulations showing that the AGC could track input power changes in the range from -44 to +11 dBm introduced to the VGAfs 100 Ω differential input impedance. The VGA has a measured bandwidth of 18 MHz and input referred noise of 3.5 nV/√Hz. It can directly drive a capacitive load of 23 pF consuming 4 mA from a 3V supply.

16:00-16:20

Fast Settling VGA for Eddy Currents Non-Destructive Testing with an Array of Magneto Resistors

Diogo Caetano, Fábio Rabuske, David Oliveira, Taimur Rabuske, Jorge Fernandes and Moisés Piedade

INESC-ID Lisboa, Instituto Superior Técnico, Universidade de Lisboa, Lisboa, Portugal

This paper presents a low noise CMOS circuit for precise reading of an array of magnetoresistive sensors. The settling time of the low frequency AC coupled amplifier defines the reading speed for the sensors, being usually very long due to the large time constants. We present a fast settling mechanism that momentarily reduces the resistance defining the high-pass filter pole and changes it back to the initial value when the signal crosses zero, to avoid glitches. A logic circuit for zero cross detection based on a reference signal is implemented together with a delay matching circuit. This technique has been validated by measurements in a simplified discrete prototype and by simulation in an ASIC implemented in AMS 0.35 μm technology. The ASIC has a simulated 30 nV/√Hz noise at 1 kHz, a bandwidth from 100 Hz to 10 MHz, and a settling time of T/2, being T the period of the signal.

16:20-16:40

Multilevel Outphasing Power Amplifier System with a Transmission-Line Power Combiner

Mikko Martelius1, Kari Stadius1, Jerry Lemberg1, Tero Nieminen1, Enrico Roverato1, Marko Kosunen1, Jussi Ryynänen1, Lauri Anttila2 and Mikko Valkama2

1Department of Micro- and Nanosciences, Aalto University, Espoo, Finland, 2Department of Electronics and Communications Engineering, Tampere University of Technology, Tampere, Finland

This paper presents a multilevel outphasing power amplifier (PA) system consisting of eight class-D unit PAs on 28 nm CMOS and an off-chip transmission-line power combiner. The combiner, implemented on PCB with microstrip lines, was designed to operate at 1.8 GHz frequency and filter out the third and fifth harmonics generated by the PAs. The combiner layout was designed so that the line spacing increases towards the output to reduce coupling, while the lines are equal in length. The simulated maximum output power is 32.3 dBm (1.71 W) with an efficiency of 34.4%. With 20 MHz and 100 MHz LTE signals, average efficiencies of 15.2% and 15.1% were achieved, respectively.

16:40-17:00

An Offset Reduction Technique for Dynamic Voltage Comparators

Andres Amaya, Rodolfo Villamizar and Elkim Roa

UIS - Universidad Industrial de Santander, Bucaramanga, Colombia

This paper presents a technique to reduce offset voltage of a dynamic comparator. Contrary to conventional way of measuring offset, the proposed technique is based on phase measurement of comparator output. A full-digital implementation is used to measure phase without impacting offset accuracy. Simulation results show a reduction of more than ten times in the comparator offset with a small increment in power consumption. The technique can be used during normal operation requiring less than 500ns to finish calibration, so that there is not need to break the communication link associated to the comparator. The circuit has been implemented in a 130nm TSMC standard CMOS process.

15:20-17:00Sensors/Systems and MEMS I
Room 02.2
Chair: Elena Blokhina
15:20-15:40

ALD-Based 3D-Capacitors for Harsh Environments

Dorothee Dietz, Yusuf Celik, Andreas Goehlich, Holger Vogt

Fraunhofer Institute for Microelectronic Circuits and Systems IMS, Finkenstr. 61, 47057 Duisburg, Germany

Passive components like capacitors for harsh environments become more and more important, e. g. in the field of deep drilling, aerospace or in the automotive industry. They have to withstand temperatures up to 300 °C with a good performance concerning leakage current, breakdown voltage and capacitance density. The whole process flow has to be CMOS-compatible in order to offer the possibility for CMOS-integration. A highly n-doped Sisubstrate (doping concentration about 1020 cm-3, phosphorus) acts as bottom electrode to keep the process flow as simple as possible. The capacitors are 3D-integrated to achieve a high capacitance density. For the dielectric layer and the upper electrode, atomic layer deposited (ALD) materials are used. The combination of the medium- and high-k dielectrics and the electrode materials are optimized, as well as some of the ALDprocesses, to reach an optimum in leakage current and breakdown voltage. At a bias voltage of 3 V at room temperature, the leakage current amounts about 5 pA/mm², at 300 °C about 40 pA/mm². Up to ± 15 V for room temperature, respectively up to ± 10 V for 300 °C, no soft-breakdown is observed, indicating the absence of significant Fowler-Nordheim tunneling.

15:40-16:00

Implementation of a Design Concept of a Moulded, Soft Battery Cell

Victoria Oguntosin, Slawomir J. Nasuto and Yoshikatsu Hayashi

Brain Embodiment Lab, School of Systems Engineering, University of Reading, United Kingdom

In this work, a moulded electrochemical battery cell made completely of soft silicone rubber is designed. A wet cell battery, similar to the galvanic cell, was fabricated using soft and stretchable silicone rubber impregnated with filler metal powders. The capacity to produce electrical power is demonstrated by measuring the voltage. The battery can produce between 0.2 - 0.4V per cell. This demonstrated concept has application in using the skin of a soft robot in powering low energy sensors attached to a soft robot and in medical applications. The moulded soft cells can be connected in series and parallel to increase the current or voltage capacity. Finally, the possible potential applications of this demonstrated concept is discussed.

16:00-16:20

SPAD-Based 3D Sensors for High Ambient Illumination

Maik Beer, Bedrich J. Hosticka, and Rainer Kokozinski

Fraunhofer Institute for Microelectronic Circuits and Systems (IMS), Finkenstrasse 61, 47057 Duisburg, Germany

With the possibility of fabricating single-photon avalanche diodes in standard CMOS processes, arrays for range imaging applications have been developed. Proper operation in high ambient illumination environments is one of the major issues of scannerless sensors published so far. In this paper a theoretical study of the direct and indirect working principle regarding high ambient illumination is shown. Further, new concepts based on these principles to reduce the sensitivity to ambient light are presented.

16:20-16:40

Design of a Variable Resolution CMOS Image Sensor for a Smart Security System

Yongjun Cho, Hyundong Kim, Youngcheol Sohn, Jihwan Oh, and Minkyu Song

Dept. of Semiconductor Science, Dongguk University, Seoul, KOREA

Recently, CMOS Image Sensor (CIS) is now widely used in the field of security system. Normally, in an emergency state, a security system must record a picture in a high resolution mode. On the contrary, in a normal state without any events or accidents, it can take a picture in a low resolution mode. In this paper, a variable resolution CIS is described to implement a smart security system. A variable resolution CIS chip has been fabricated with a Samsung 0.13μm CMOS technology and it satisfied a QVGA resolution (320~240) with a pitch of 5.0 μm and a 4- Tr active-pixel sensor structure. The measured frame rate is 60 frame/s with a power consumption of 9.8mW at 2.8V(Analog)/1.5 V(Digital) power supply. When the variable resolution technique is adopted, the power consumption is about 2.7mW at the low resolution mode. Further, the chip area is about 19mm2.

16:40-17:00

Optimization of the thermal drift caused by Joule heating in piezoresistive pressure sensor

Abdelaziz Beddiaf1, Fouad Kerrour2, Sami Bedra1, Lazher Merouani1, Salah Kemouche2

1Faculty of Science and Technology, Khenchela University, Algeria, 2University of Constantine 1, MoDERNa Laboratory, Constantine, Algeria

The thermal drift provoked by the Joule heating in piezoresistive pressure sensors is a major source of imprecision for their applications requiring high accuracies measurements. This thermal drift affects greatly the performance of the such sensors. This work derives an accurate numerical model for optimization and predicting the temperature in piezoresistive pressure sensors due to the electric heater in its piezoresistors. In this case, by using the solution of 2-D heat transfer equation considering Joule heating in Cartesian coordinates for the transient regime, we determine how the temperature affects the sensor during the applying a supply voltage. In addition, the present study puts emphasis on the geometric effect of parameters on these characteristics to optimize the sensors performance. Finally, this study allows us to predict the sensor behaviour against temperature rise due to the Joule heating and to minimize this effect by optimizing the geometrical parameters and by reducing the applied voltage.

P95 - Abdelaziz Beddiaf, "Optimization of the thermal drift caused by Joule heating in piezoresistive pressure sensor"
15:20-17:20Emerging Technologies and Applications II
Room 02.3
Chair: João Pedro Oliveira
15:20-15:40

Large area silicon photomultipliers allow extreme depth penetration in time-domain diffuse optics

E. Martinenghi, A. Dalla Mora, L. Di Sieno, S. Konugolu Venkata Sekar, D. Contini and A. Pifferi

Dipartimento di Fisica, Politecnico di Milano, Piazza Leonardo da Vinci 32, I-20133 Milano, Italy

We present the design of a novel single-photon timing module, based on a Silicon Photomultiplier (SiPM) featuring a collection area of 9 mm2. The module performs Single-Photon Timing Resolution of about 140 ps, thus being suitable for diffuse optics application. The small size of the instrument (5 cm x 4 cm x 10 cm) allows placing it directly in contact with the sample under investigation, maximizing that way the signal harvesting. Thanks to that, it is possible to increase the source detector distance up to 6 cm or more, therefore enhancing the penetration depth up to an impressive value of 4 cm and paving the way to the exploration of the deepest human body structures in a completely non-invasive approach.

15:40-16:00

Improved stability of organic solar cells by crosslinking of the electron-donor polymer

Joana Farinhas1, Ricardo Oliveira1, Ana Charas1, Jorge Morgado1,2

1lnstituto de Telecomunicações, Lisbon, Portugal, 2Instituto Superior Técnico, University of Lisbon, Portugal

We fabricated organic photovoltaic cells with enhanced performance stability measured after temperature annealing at 100 °C and over a period of 24 days at room temperature. This improvement was achieved upon chemical cross-linking of the photo-active layer of the devices, combining a cross-linkable polymer and a fullerene, PC61BM. The cells efficiency decayed by up to 14 % upon heating at 100 °C and by 37 % after the 24 days period, while the efficiency of control devices based on noncross-linked layers was decreased by 58 % and 55 %, respectively.

16:00-16:20

Diamond / SiC heterojunctions

Debarati Mukherjee1, Joana C. Mendes1, Luis N. Alves1, Miguel Neto2, Filipe J. Oliveira2

1Instituto de Telecomunicações, Campus Universitário de Santiago, 3810-193 Aveiro, Portugal, 2CICECO, Department of Materials and Ceramic Engineering, University of Aveiro, 3810-193 Aveiro, Portugal

Diamond and SiC are wide bandgap (WBG) materials which can be used to fabricate high power devices with improved performance. The combination of these materials into one single device is expected to bring some benefits, like a better thermal management with a corresponding increase in the operating power. Diamond films deposited by Chemical Vapor Deposition (CVD) can be doped with boron, making them p-type semiconductors. Diamond films deposited on foreign substrates are intrinsically polycrystalline, so the quality of the interface, determined by deposition conditions and seeding method, plays a critical role in the heterojunction characteristics, impacting both reverse current and breakdown voltage. This work reports the fabrication and characterization of p-diamond / n-SiC heterojunctions. P-type polycrystalline diamond (PCD) films were deposited directly on the surface on n-type SiC commercial wafers by Hot Filament CVD (HFCVD) using different seeding techniques. I-V characteristics of the obtained heterojunctions were measured at room temperature and the quality and morphology of the diamond films were assessed by scanning electronic microscopy (SEM) and Raman spectroscopy. The influence of the different seeding techniques on the I-V characteristics is discussed.

16:20-16:40

Analysis of Light Emitters SRO-based to be Integrated on all-silicon Optoelectronic Circuits

J. Alarcón-Salazar1, M. A. Vázquez-A.1, E. Quiroga-González2, I. E. Zaldívar-Huerta1 and M. Aceves-Mijares1

1Instituto Nacional de Astrofísica, óptica y Electrónica (INAOE), Depto. de Electrónica, Puebla, México, 2

Benemérita Universidad Autónoma de Puebla (BUAP), Instituto de Física, Puebla, México

This work presents the analysis of two light emitting capacitors compatible with silicon technology. Both structures use silicon rich oxide obtained by low-pressure chemical vapor deposition as active material. One structure uses a single layer with a textured surface substrate, which improves carrier injection. The second device is a multilayered structured deposited on a polished surface substrate. Both devices are studied and their emission and electrical characteristics are highlighted in order to elucidate on the best option to be integrated in all-silicon optoelectronic circuits.

16:40-17:00

Chip-Level CMOS Co-Integration of ReRAM-Based Non-Volatile Memories

Elmira Shahrabi, Jury Sandrini, Behnoush Attarimashalkoubeh, Tugba Demirci, Mahmoud Hadad and Yusuf Leblebici

This work reports a technique to fabricate ReRAM crossbar arrays co-integrated with fully finished 180nm CMOS technology chips. The proposed integration method enables lowcost ReRAM-CMOS integration and allows the rapid prototyping of complete memory systems. We propose to use W plugs, already present as vias in CMOS technology, as the ReRAM bottom electrodes. The resistance switching layer, WOx, is obtained by the mask-free rapid thermal oxidation of the W plug surface. With this method, we are able to fabricate 280nm nonvolatile memory devices without any additional high-resolution lithography. The integrated memory devices operate at 300 μA, with a high resistance state of 0.6MΩ and low resistance state of 4 kΩ. The electrical characteristics confirm the possibility to integrated non-volatile memories on the back-end-of-the-line of standard CMOS chips, enabling low-cost integration of the memory components with the CMOS driving circuitry.

15:20-17:20EDA Competition - II
Auditório
Chair: Ricardo Martins
15:20-15:50

SCALES: A High Speed Simulator Tool for Pipeline A/D Converters

Carlos Silva1, Jorge Guilherme1,2, Nuno Horta3

1Instituto Politécnico de Tomar - Tomar, Portugal, 2Instituto de Telecomunicações - Lisbon, Portugal, 3Instituto de Telecomunicações, Instituto Superior Técnico, Lisboa, Portugal

This paper presents the latest version of the pipeline ADC simulator tool (SCALES), a high speed analog behavior simulation tool for analog-to-digital converters. This tool allows topology selection and the digital calibration of the main frontend blocks. Additionally, the tool generates also the required Verilog code to implement the digital calibration block. Several block non-linearities are included in the simulation, such as gain and offset errors, capacitor mismatch, thermal noise, parasitic capacitances, settling errors and other important error sources. The tool has been used and validate in several high performance pipeline ADCs, up to 16 bits resolution.

15:50-16:20

A Novel Polygon-Based Circuit Extraction Algorithm for Full Custom Designed MEMS Sensors

Axel Hald1, Johannes Seelhorst1, Mathias Reimann1, Jürgen Scheible2 and Jens Lienig3

1Automotive Electronics, Robert Bosch GmbH, Tübinger Str. 123, 72762 Reutlingen, Germany, 2Reutlingen University, Robert Bosch Center for Power Electronics, 3Dresden University of Technology, Institute of Electromechanical and Electronic Design, www.ifte.de

In contrast to IC design, MEMS design still lacks sophisticated component libraries. Therefore, the physical design of MEMS sensors is mostly done by simply drawing polygons. Hence, the sensor structure is only given as plain graphic data which hinders the identification and investigation of topology elements such as spring, anchor, mass and electrodes. In order to solve this problem, we present a rule-based recognition algorithm which identifies the architecture and the topology elements of a MEMS sensor. In addition to graphic data, the algorithm makes use of only a few marking layers, as well as net and technology information. Our approach enables RC-extraction with commercial field solvers and a subsequent synthesis of the sensor circuit. The mapping of the extracted RC-values to the topology elements of the sensor enables a detailed analysis and optimization of actual MEMS sensors.

16:20-16:50

Statistically-Aided Electronic Design Environment

Carlos Gil Soriano, Pablo Ituero

Dpto. de Ingeniería Electrónica, ETSI Telecomunicación, Technical University of Madrid, Spain

This work presents SAEDE (Statistically-Aided Electronic Design Environment), a framework targeted to perform advanced statistical analysis within an ASIC design workflow, linking together circuit performance with technological parameters. A driving example, the design of a 10-stage delay line, is conducted. The study goals are two-fold: extract a circuit performance metric, the spread of the stage-delay, and determine its most sensitive BSIM4 transistor parameters. To achieve these goals, two statistical tools, new to ASIC design work-flow, have been used: Skew-Normal inference and BAHSIC feature selection. Consistent results are obtained, relating BSIM4 parameters to circuit performance impossible to grasp by analytical terms.

16:50-17:20

SIDe-O: A Toolbox for Surrogate Inductor Design and Optimization

F. Passos, E. Roca, R. Castro-López, F. V. Fernández

Instituto de Microelectrónica de Sevilla, IMSE, CNM (CSIC, Universidad de Sevilla), Seville, Spain

This paper presents SIDe-O, a CAD tool developed for the design and optimization of integrated inductors based on surrogate modeling techniques. This tool provides a solution to the problem of accurately and efficiently optimizing the design of inductors. The models used present less than 1% error when compared to EM simulations while reducing the simulation time by several orders of magnitude. Additionally, the tool provides the ability to create new surrogate models for different technologies and inductor topologies. The tool also allows the creation of an S-Parameter file that accurately describes the behavior of the inductor for a given range of frequencies, which can later be used in SPICE-like simulations.

THURSDAY, June 30th
9:00-10:40Power ICs II
Auditório
Chair: Alberto Gola
9:00-9:20

A CMOS compact differential band-gap voltage reference with programmable output

S. Del Cesta1, P. Bruschi1, A.N. Longhitano1, R. Simmarano2and M. Piotto3

1Dipartimento di Ingegneria dell’Informazione, University of Pisa, Pisa - Italy; 2Sensichips srl, Latina - Italy; 3IEIIT - Pisa, CNR, Pisa, Italy

A modified band-gap circuit capable of producing programmable output differential reference voltage is described. Analysis of the effects of the amplifier noise and offset on the reference voltage is performed, obtaining a compact formula of general validity. A prototype, based on a switched capacitor amplifier with continuous time output, has been designed using the UMC 0.18 um CMOS process. The circuit produces three digitally selectable output differential voltages in the range 1.22-2.8 V and is capable of sourcing/sinking currents up to of 1 mA. Electrical simulations show that the temperature stability is 38 ppm/°C while the standard deviation of output voltage spread is nearly 0.4%.

9:20-9:40

Layout Capacitive Coupling and Structure Impacts on Integrated High Voltage Power MOSFETs

Lin Fan, Arnold Knott and Ivan Harald Holger Jørgensen

Department of Electrical Engineering, Technical University of Denmark, Kgs. Lyngby, Denmark

The switching performances of the integrated high voltage power MOSFETs that have prevailing interconnection matrices are being heavily influenced by the parasitic capacitive coupling of on-chip metal wires. The mechanism of the side-byside coupling is generally known, however, the layer-to-layer coupling and the comparison of the layout impacts have not been well established. This paper presents modeling of parasitic mutual coupling to analyze the parasitic capacitance directly coupled between two on-chip metal wires. The accurate 3D field solver analysis for the comparable dimensions shows that the layer-to-layer coupling can contribute higher impacts than the well-known side-by-side coupling. Four layout structures are then proposed and implemented in a 0.18 μm partial SOI process for 100 V integrated power MOSFETs with a die area 2.31 mm2. The post-layout comparison using an industrial 2D extraction tool shows that the side-by-side coupling dominated structure can perform better than the layer-to-layer coupling dominated structure, in terms of on-resistance times input or output capacitance, by 9.2% and 4.9%, respectively.

9:40-10:00

Investigation of Stepwise Charging Circuits for Power-Clock Generation in Adiabatic Logic

Himadri Singh Raghav, Vivian A. Bartlett and Izzet Kale

Applied DSP and VLSI Research Group, Department of Engineering, University of Westminster, London, W1W 6UW, United Kingdom

The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider stepwise charging strategies (2, 3, 4, 5, 6, 7, and 8-step) based on tank-capacitor circuits, comparing them in terms of their energy recovery properties and complexity. We show that energy recovery achievable depends on the tank-capacitor size. We also show that tank-capacitor sizes can be reduced as their number increases concluding that combined tank capacitance (CTT) versus load capacitance (CL) ratio is the significant parameter. We propose that using a CTT/CL ratio of 10 and using a 4-step charging power-clock constitute appropriate trade-offs in practical circuits.

10:00-10:20

Design of a Radiation-Hardened Curvature Compensated Bandgap Reference Circuit

António Fitas, Nuno Horta and Jorge Guilherme

Instituto de Telecomunicações, Instituto Superior Técnico, Lisboa, Portugal

This work presents the design and dimensioning of of a bandgap voltage reference - BGV - generator with second order compensation. The developed circuit provides a steady voltage at the output, stable to noise, temperature and power source drifts, which functions as a reference voltage for other circuit blocks. The main purpose of the work is to obtain a BGV generator with a voltage of 1.25V and performances which can improve a previous proposed circuit. The FOM that primarily characterize the circuit and that will be the focus of improvement are the PSRR, the TC and the current consumption. The achieved results by the proposed circuit are a PSRR of -81.93 dB, a TC of 2 ppm/°C and a current consumption of 2.34 mA.

10:20-10:40

Calibration-free 1052μm2 Power Supply Monitor

Hernán Cerqueira, Pablo Ituero and Marisa López-Vallejo

Dpto. de Ingeniería Electrónica, ETSI Telecomunicación, Universidad Politécnica de Madrid, Ciudad Universitaria s/n, 28040 Madrid, Spain

The presence of noise in the power supply line in the form of ripples or spikes jeopardizes the behavior of electronic circuits. One solution to this problem is the use of power supply monitors that flag a signal whenever a hazardous situation is detected. In this paper we present a low area power supply monitor that detects under- and overshoots and does not require neither external reference nor calibration. It is based on the use of a bandgap core as voltage detector which proved to be especially robust against temperature and process variations. The monitor has been designed with a 40nm commercial technology, and is characterized by a 1052 μm2 area, 6.4 pJ of energy consumption per measurement. It is able to sense ±40 mV for over- and undershoots without the need of calibration and with a maximum response latency of 1.7 ns for the worst technology corner.

9:00-10:40Digital Signal Processing
Room 02.1
Chair: Jorge Guilherme
9:00-9:20

Non-Recursive Method for Motion Detection from a Compressive-Sampled Video Stream

Marco Trevisi, Ricardo Carmona-Galán and Angel Rodríguez-Vázquez

Instituto de Microelectrónica de Sevilla (IMSE-CNM), CSIC-Universidad de Sevilla, Spain.

This paper introduces a non-recursive algorithm for motion detection directly from the analysis of compressed samples. The objective of this research is to create an algorithm able to detect, in real-time, the presence of moving objects over a fixed background from a compressive-sampled greyscale video stream. Many difficulties arise using this type of algorithm because it violates the fundamental principles of compressive sensing reconstruction that lie beneath traditional recursive methods. Recursive reconstruction methods even if accurate need large amounts of time and resources because they aim to retrieve all of the information contained within a scene. Our method is based on two key considerations. The first is that the targeted information of a moving element compared to a fixed background is really small. The second is an appropriate choice of a sub-Gaussian compressive sampling strategy. Our aim is to reduce the focus of general reconstruction in order to retrieve only objects of interest. This algorithm can be used to process compressed samples derived from a video stream with a speed of 100fps. This makes possible to detect the presence of moving objects directly from compressed samples with limited resources.

9:20-9:40

Statistical tests to determine spatial correlations in the response behavior of PUFs

Benjamin Willsch, Julia Hauser, Stefan Dreiner, Andreas Goehlich and Holger Vogt

Fraunhofer Institute for Microelectronic Circuits and Systems, IMS, Finkenstraße 61, 47057 Duisburg, Germany

The level of security provided by physically unclonable functions (PUFs) strongly depends on the unpredictability of its challenge-response behavior. Systematic variation in the properties of a PUF might introduce correlations in the output bits. The mutual dependence of response bits is typically not detected by conventional methods, thus leaving the PUF vulnerable to prediction attacks. New methods accounting for the spatial distribution of response bits are presented, allowing to detect security leaks due to correlation effects at device level. The presented methods are easily applicable to a wide-range of array-based PUFs.

9:40-10:00

Impact of the AER-Induced Timing Distortion on Spiking Neural Networks Implementing DSP

Thomas MESQUIDA1, Alexandre VALENTIAN1, David BOL2 and Edith BEIGNE1

1Université Grenoble Alpes, CEA, LETI, MINATEC Campus, 38054, Grenoble, France; 2ICTEAM Institute, Université catholique de Louvain, Louvain-la-Neuve, Belgium

Spiking Neural Networks are considered to be the latest generation of artificial neural networks. They rely on principles inspired from brain operation and use coding strategies based on relative timings and/or rates to transport information. Implementing large hardware networks requires the use of Address Event Representation (AER) which affects the inter-spike timings. This paper focuses on various mathematical AER models and their influence on spike rate coding in Signal Processing applications implemented with SNN. For the most basic M/M/1 queue model, there is no effect on the results given by the considered benchmark multiplier operator, whereas for more realistic M/D/1 and M/G/1 models, the relative error comparing to Poisson process is respectively below 3% and 3.8% for realistic operations.

10:00-10:20

A Tone Mapping Algorithm Suited for Analog-Signal Real-Time Image Processing

Lan Shi1, David Hadlich1, Christopher Soell1, Thomas Ussmueller2 and Robert Weigel1

1Institute for Electronics Engineering, University of Erlangen-Nuremberg, Erlangen, Germany; 2Institute for Mechatronics, University of Innsbruck, Innsbruck, Austria

This work presents a Tone Mapping Operator (TMO) which adjusts the High Dynamic Range (HDR) of image sensor data to the limited dynamic range of conventional displays with analog signal processing. It is based on Photographic Tone Reproduction (PTR) and suitable for analog circuit design in a CMOS image sensor in order to reduce the hardware cost and operation time for real-time image processing. For this reason, the characteristic advantage and calculation limitation of analog technology are considered in the TMO algorithm proposal. Furthermore, the appropriate modelling is built and simulated in Verilog-A. The function of the algorithm is feasible for analog processing. The frequency of the analog TMO is upper 52MHz while it consumes 55mW. The simulation results of test images are compared with the digital global TMO and the proposed analog TMO provides a reasonable similar dynamic range compression.

10:20-10:40

Lightweight Ciphers Based on Chaotic Map - LFSR Architectures

M. Garcia-Bosque, C. Sánchez-Azqueta, G. Royo, S. Celma

Group of Electronic Design, Universidad de Zaragoza, Zaragoza, Spain

In this paper, we propose and analyze two different stream ciphers based on a Skew Tent Map and a Modified Logistic Map respectively. In order to improve the randomness of these systems, a single method for increasing the period length of the generated sequences has been applied. The results prove that the randomness of these systems can be severally increased by using this method, making these systems suitable for secure communications.

9:00-10:40Design techniques for analog and digital circuits
Room 02.2
Chair: Günhan Dündar
9:00-9:20

An Efficient Methodology to Characterize the TSPC Flip Flop Setup Time for Static Timing Analysis

Sayyaparaju Sagar Varma, Arvind Sharma, Bulusu Anand

Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, India

Static timing analysis (STA), which is a part of design automation requires the generation and storage of delay values for combinational standard cells and the setup and hold time values for sequential cells at numerous corners in the form of a Look Up Table (LUT). This paper proposes a novel approach for LUT generation of sequential standard cells by developing a model for the setup time. The model uses the input data transition time (TR) and the output capacitance (CL) as its variables with two fitting parameters. The model’s validity is verified through simulations in Cadence Virtuoso and using this model, it is shown that it reduces the number of simulations needed for the generation of a 6 × 6 LUT by 91.67%, while having an average percentage error of 2.28%. Also, the dependence of the fitting parameters on the sizing of the devices and their relation with process, voltage and temperature variations is shown and verified.

9:20-9:40

A Novel Energy-Efficient Self-Correcting Methodology Employing INWE

Chaudhry Indra Kumar1, Arvind Sharma1, Sandeep Miryala2 and Anand Bulusu1

1Indian Institute of Technology Roorkee; 2Nikhef, Amsterdam

Operating VLSI circuits at near/sub-threshold region is emerging as the most important technique for low power applications. However, due to the increasing variability in subthreshold regime, system performance and yield is at stake. Therefore, improved circuit techniques are needed with low power overhead which can essentially improve the yield. This paper presents a timing error Self Correcting Flip-Flop (SCFF) operating at near threshold voltage. The proposed SCFF automatically corrects timing faults in sequential elements and datapaths, thereby reducing performance degradation due to variations and improves yield. The proposed technique uses Inverse Narrow Width effect (INWE) for performance optimization. The proposed methodology is evaluated by considering few custom circuits along the data-path. The simulation results show that the proposed SCFF design achieves better yield ratio for a given frequency specification, ~0.33 at 0.4v and ~0.32 at 0.35v supply voltage against existing error detection and correction methods.

9:40-10:00

IIP Framework: A Tool for Reuse-Centric Analog Circuit Design

Benjamin Prautsch1, Uwe Eichler1, Sunil Rao1, Björn Zeugmann1, Ajith Puppala1, Torsten Reich1 and Jens Lienig2

1Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS, Dresden, Germany; 2Dresden University of Technology, Dresden, Germany

Current design of analog integrated circuits is still a time-consuming manual process resulting in static analog blocks which can hardly be reused. In order to address this problem, a new framework to ease reuse-centric bottom-up design of analog integrated circuits is introduced. Our IIP Framework (IIP: Intelligent Intellectual Property) enables the development of highly technology-independent analog circuit generators applicable in multiple design environments. IIP Generators are parameterizable descriptions of each view of an analog block, i.e., layout, schematic, and symbol. They allow the adaptation of complex layouts within seconds to minutes in order to incorporate hardly estimable parasitics and further considerations into the design flow. Due to the abstract generator description, valid design data is created for very different technologies such as 28 nm and 180 nm bulk CMOS, 28 nm FDSOI, and others. The design experiment shows that procedural generators can be an effective tool for the efficient design of analog integrated circuits.

10:00-10:20

Moving beyond Traditional Electronic Design Automation: Data-driven Design of Analog Circuits

Xiaowei Liu and Alex Doboli

Department of Electrical and Computer Engineering, State University of New York at Stony Brook, Stony Brook, NY 11794-2350

Understanding the relation between the characteristics of the referenced ideas (as expressed by the cited papers) and the expected impact of a new design (as measured by the received citation count) is important in maximizing the outcomes of the spent design effort, time, and resources. This paper presents a new methodology and the related metrics and procedures to analyze this connection. The approach was utilized to study the distinguishing features of highly-cited papers on switched capacitor filter design. A set of pattern specific to these papers are discussed in the paper.

10:20-10:40

A High-Gain, High-Speed Parametric Residue Amplifier for SAR-Assisted Pipeline ADCs

Pydi Ganga Bahubalindruni1,3, Joao Goes2 and Pedro Barquinha3

1ECE department, IIIT-Delhi, Okhla Industrial Estate, Phase III, New Delhi, India - 110020; 2Department of Electrical Engineering, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa and CTS-UNINOVA, 2829-516 Caparica, Portugal. 3i3N/CENIMAT, Department of Materials Science, Faculty of Science and Technology, Universidade NOVA de Lisboa and CEMOP/UNINOVA, Campus de Caparica, 2829-516 Caparica, Portugal

This paper presents a high-speed and high-gain dynamic residue amplifier for two-stage SAR-assisted pipeline ADC. Parametric amplification technique is incorporated in the residue amplifier to enhance the gain, in order to meet the industrial requirements of the residue amplifier of an ADC with ENOB ≥ 10.5 bits. From simulations the proposed circuit has shown a gain of 22.05 dB and a power consumption of 0.31mW, at an operating frequency of 1.75 GHz when VDD is 1.2V and CL is 150 fF in a standard 65nm CMOS technology.

9:00-10:40 RF and microwave modeling and analysis
Room 02.3
Chair: Ralf Sommer
9:00-9:20

Analysis of Phase-Locked Loops using the Best Linear Approximation

Dries Peumans, Adam Cooman and Gerd Vandersteen

During the early design stage of Phase-Locked Loops, linear models are thoroughly used to analyse the steadystate behaviour. In reality, the envisioned linear performance is degraded due to nonlinearities present in the actual implementation. Lately, a nonlinear modelling technique based on the Best Linear Approximation has been developed which allows to verify the validity of this linear model and, in addition, permits to characterise the nonlinear distortions present in the system. Incorporating this Best Linear Approximation in the design stage allows to intuitively analyse the nonlinear behaviour of the Phase- Locked Loop.

9:20-9:40

Frequency-Dependent Parameterized Macromodeling of Integrated Inductors

F. Passos1, E. Roca1, R.Castro-López1, F.V. Fernández1, Y. Ye, D. Spina2, T. Dhaene2

1Instituto de Microelectrónica de Sevilla, IMSE, CNM (CSIC, Universidad de Sevilla), Seville, Spain; 2Department of Information Technology, IBCN, Ghent University - iMinds, Ghent, Belgium

Integrated inductors are one of the most important passive elements in radio frequency design, due to their wide usage in wireless communication circuits. Typically, electromagnetic simulators are used in order to estimate the inductors performance with high accuracy as a function of the inductor geometrical and electrical parameters. Such simulations offer high-accuracy, but are computationally expensive and extremely time consuming. In this paper, a frequency-dependent parameterized macromodeling technique is adopted in order to overcome this problem. The proposed approach offers a high degree of automation, since it is based on sequential sampling algorithms, high efficiency and flexibility: a continuous frequency-domain model is given for each value of the chosen inductors parameters in the design space.

9:40-10:00

Distortion Contribution Analysis of strongly non-linear analog circuits

Adam Cooman, Piet Bronders and Gerd Vandersteen

A Distortion Contribution Analysis (DCA) determines the contributions of each sub-circuit to the total distortion generated by an electronic circuit in a simulation. The results of the DCA allow the designer of the circuit to effectively reduce the distortion. Recently, a DCA based on the Best Linear Approximation (BLA) was introduced. In this approach, the non-linear subcircuits are modelled using a linear approximation. The nonlinear distortion is represented as an additive noise source. Combining the BLA with the concepts of a noise analysis yields a DCA that works with realistic, modulated excitation signals instead of a one or two-tone excitation. Up till now, BLA-based DCA has only been applied to weakly non-linear circuits. In this paper, it is extended and applied to a strongly non-linear circuit.

10:00-10:20

Multiresolution modelling of cavity resonators in microwave systems

Brigita Sziová1, Szilvia Nagy2, András Fehér 2and János Pipek3

1Department of Informatics, Széchenyi István University,Gy?or, Hungary; 2Department of Telecommunications, Széchenyi István University, Gy?or, Hungary; 3Department of Theoretical Physics, Budapest University of Technology and Economics, Budapest, Hungary

Multiresolution analysis or wavelet analysis provides a toolbox not only for signal processing, but also for synthesis of complex systems. Wavelets can be used for modeling complex parts of microwave circuits, such as cavity resonators. The differential equations describing the physical behavior of the device can be discretized using multiple resolutions simultaneously, i.e., high resolutions, where the details of the geometry demand it, and low resolutions, where the geometry is smooth. Using wavelet analysis offers the possibility of systematic and adaptive refinement, where the result is not sufficiently precise. Our method gives an approximation for the error of the solution in order to make it possible to decide, whether refinements are necessary.

10:20-10:40

Efficient and Automated Generation of Multidimensional Design Curves for Coupled-Resonator Filters using System Identification and Metamodels

Matthias Caenepeel, Francesco Ferranti, Yves Rolain

Vrije Universiteit Brussel (VUB), Department of Fundamental Electricity and Instrumentation, 1050 Brussels, Belgium

The design of coupled-resonator microwave bandpass filter is very often based on the physical implementation of a coupling matrix by correctly dimensioning the filter (geometrical) design parameters. An initial dimensioning is carried out using the design curves that describe the inter-resonator coupling parameter and external quality factor as a function of (geometrical) design parameters of a coupled-resonator pair and a single loaded resonator, respectively. These curves are usually generated using electromagnetic (EM) simulations. In order to minimize the number of EM simulations, these curves often consider only a single design parameter, while in reality several design parameters influence the inter-resonator coupling parameter and external quality factor. In this paper, a metamodeling method is used to generate multidimensional design curves with a minimal number of EM simulations, while maintaining a good accuracy. Moreover, their generation process is fully automated. The automated generation of multidimensional design curves for a coupled hairpin resonator filter validates the proposed method.

13:20-15:00 Sensors/Systems and MEMS II
Auditório
Chair: Franco Maloberti
13:20-13:40

Design of an electrophoretic module for protein separation

Andrea Capuano1,2, Andrea Adami1, Viviana Mulloni1 and Leandro Lorenzelli 1

1Fondazione Bruno Kessler - FBK, Trento, Italy; 2Università degli Studi di Trento, Trento, Italy

In this paper we discuss the model, theory and design optimization of an electrophoretic separation system configured as a split flow thin fractionation, which can be used for protein separation from milk samples as part of an integrated analytical system for detection of contaminants or pathogens. In particular, we describe the design and the fabrication strategy to achieve optimal separation and a sample-processing throughput in the order of ml/min.

13:40-14:00

Power Analysis of Local Transmission Technologies

Darshana Thomas, Ross McPherson and James Irvine

University of Strathclyde, Department of Electronic & Electrical Engineering, Glasgow, United Kingdom

With the number of Internet of Things (IoT) devices expected to explode to over 20 Billion devices by 2020, it is vital that efficient communication technologies are used. While ideally a single technology would emerge to simplify deployment, in practice the varying power and bandwidth requirements of different devices has led to an industry split over communication technologies, and while a number of new technologies have been designed with IoT in mind, commercial imperatives have meant that existing wireless protocols, in particular Wi-Fi and 433 MHz AM, remain the most prevelent. This article outlines the power usage of these two most common protocols, and considers power aspects of using each protocol in an IoT setting with experiments carried out with real world devices used in current products.

14:00-14:20

V2O5/4H-SiC Schottky Diode as a high performance PTAT sensor

G. Pangallo, S. Rao, F.G. Della Corte, L. Di Benedetto and A. Rubino

1Department of Information Engineering, Infrastructures and Sustainable Energy, DIIES, Università degli studi "Mediterranea" Reggio Calabria, 89122, Italy; 2Department of Industrial Engineering, Università di Salerno, Fisciano (SA), Italy

A proportional to absolute temperature sensor (PTAT) based on V2O5/4H-SiC (divanadium pentoxide/4H polytype of silicon carbide) Schottky diodes is presented. The linear dependence between the voltage differences across two constant-current forward biased diodes on temperature has been used for thermal sensing in the wide temperature range from T=147 K up to 400 K. A sensitivity of 307 μV/K was calculated for two constant bias currents, ID1=16 μA and ID2=608 μA.

14:20-14:40

Low Power RSSI Outdoor Localization System

Naglaa El Agroudy, Niko Joram and Frank Ellinger

Technische Universität Dresden, 01062 Dresden, Germany

This work presents a low power outdoor localization system that implements a power management technique in order to control the wakeup and sleep of the different modules in the system. Through this technique, the system achieves 6.7 μA in sleep mode. A new weighted least mean squares solution algorithm that is based on received signal strength indicator (RSSI) measurements is introduced. Both simulation and measurement results are presented. It is shown that over 50% improvement in position estimation is achieved using the proposed weighted least mean squares algorithm.

14:40-15:00

Circuit Considerations and Design for MEMS Capacitance Measurements

D. Andrade-Miceli1, P. Giounalis1, S. Gorreta2, J. Pons-Nin2, M. Dominguez-Pumar2, and E. Blokhina1

1School of Electrical, Electronic and Communications Engineering, University College Dublin, Dublin, Ireland; 2Micro and Nano Technologies Group Electronic Engineering Department, Technical University of Catalonia, Barcelona, Spain

Modern CMOS integrated technologies integrate a variety of complex multi-physics components which contribute a growing number of challenges in the circuit design. This paper is focused on the description of the requirements and technical aspects which should be considered for successful circuit design involving capacitive MEMS. To illustrate the process, the design of an input stage for a MEMS dielectric charge bipolar control method is presented.

13:20-15:00 RF, Microwave and mm-wave Circuits II
Room 02.1
Chair: Jorge Guilherme
13:20-13:40

CMOS High-Performance UWB Active Inductor Circuit

H.G. Momen1, M. Yazgi1, R. Kopru2 and A.N. Saatlo3

1Electrical-Electronics Eng. Dep., Istanbul Technical University, Istanbul, Turkey; 2Electrical-Electronics Eng. Dep., Isik University, Istanbul, Turkey; 3Electrical-Electronics Eng. Dep., Islamic Azad University, Urmia, Iran

In order to maximize efficiency of the designed gyrator-based active inductor, advanced circuit techniques are used. Loss and noise are most important features of the AIs, where they should be low enough to have high-performance device. The gyrator-C topology is used to design a new low-loss and low-noise active inductor. The gyrator-C topology is potentially high-Q and all transistors are utilized in common-source configuration to have high impedance in input-output nodes. All transistors are free of body effect. The p-type differential pair input transistors and the feed forward path are employed to decrease noise of the proposed circuit. Additionally, inductance value and quality factor are adjusted by variation bias current which gives to the device tunable capability. HSPICE simulation results are presented to verify the performance of the circuit, where the 180 nm CMOS process and 1.8 V power supply are used. The noise voltage and power dissipation are less than 2.8 nV/ √ Hz and 1.3 mW, respectively.

13:40-14:00

A Multi-Rate Clock and Data Recovery Circuit for Short-Reach Optical Links

E. Guerrero, C. Gimeno, C. Sánchez-Azqueta, J. Aguirre and S. Celma

Group of Electronic Design - Aragon Institute of Engineering Research (GDE-I3A), Universidad de Zaragoza, E-50009 Zaragoza, Spain

This paper presents a multi-rate clock and data recovery circuit with integrated adaptive equalizer. It was designed in a standard 0.18 μm CMOS technology with a single supply voltage of 1.8V and consumes 140mW. The prototype has been tested for short reach applications targeting a multi-rate 231 - 1 NRZ pseudo-random binary sequence through a 50-m stepindex plastic optical fiber (SI-POF), ranging from 400Mbit/s up to 2.5Gbit/s.

14:00-14:20

A DC-coupled 27 MHz LNA and Automatic Gain Control Amplifier on an Ultra-Thin 0.5 μm CMOS Gate Array for a Wireless Sensor System-in-Foil

Jochen Briem, Markus Gröezing and Manfred Berroth

Institute of Electrical and Optical Communications Engineering (INT), University of Stuttgart, Germany

This paper presents a DC-coupled 27 MHz low noise amplifier (LNA) and automatic gain control (AGC) amplifier on a specially processed ultra-thin 0.5 μm CMOS gate array for the RF receiver of a wireless and bendable sensor system-in-foil. As the receiver is made for amplitude shift keying (ASK) signals, it needs an AGC. An offset feedback (OSFB) control circuit is realized to compensate for offsets. As required for the application specific protocol, a short settling time is needed. Therefore a Manchester coded input signal is used. The ASK modulation is used because of circuit energy consumption reasons in the given technology. The RF receiver works without a local oscillator (LO).

14:20-14:40

Capacitive coupling analysis using double-surface ICs for low cost passive RFID tags

Lorenzo Pirrami1, Danilo Demarchi1 and Marco Mazza2

1Department of Electronics and Telecommunication (DET), Politecnico di Torino, Torino, Italy; 2Department of Electrical Engineering, Institute for Printing, University of Applied Sciences and Arts Western Switzerland, Fribourg, Switzerland

This paper introduces a new concept of liquid phase inkjet-based fabrication process for low cost, low range and high throughput Radio Frequency Identification (RFID) tags. In this research, passive chips have one pad on the top of the chip and the back of the silicon die (bulk) acting as the second pad. Such a chip can be delivered, using an inkjet-based process, onto one pad of an antenna instead to be precisely placed using flip-chip method. This allows producing RFID tag only with printing steps, reducing considerably the assembly and hence the overall costs. We demonstrate the feasibility of this approach by analyzing the capacitive coupling obtained using double-surface chips.

14:40-15:00

Design of Ultra Low Power Cascaded Inductorless LNA for Wireless Sensor Network Application

S.Vahid M.Bonehi, Arthur Ruder, Soheil Aghaie, Iyappan Subbiah, Ralf Wunderlich and Stefan Heinen

Integrated Analog Circuits and RF Systems, RWTH Aachen University, Germany

This paper presents a cascaded ultra low power LNA structure. The proposed architecture benefits from a common gate LNA as the first stage followed by indcutorless common source LNA. The complete design was implemented in a standard 130nm RF CMOS process. The design occupies 130μm× 130μm active area. The circuit operates at 2.4GHz and draws 240μm under supply voltage of 1.2V. It shows active voltage gain of 42 dB and NF of 11.2 dB after post layout simulation. Thanks to first stage common gate structure, it has input reflection coefficient better than 22 dB.

13:20-15:00 Modeling of unconventional devices and applications
Room 02.2
Chair: Giulia di Capua
13:20-13:40

A new Table Based Modelling of 28nm Fully Depleted Silicon-On Insulator (FDSOI)

Abdelgader M.Abdalla, Jonathan Rodriguez

Instituto de Telecomunicações, Department of Electronics, Telecommunications, and Informatics University of Aveiro Aveiro, Portugal

In this work, a multivariate interpolation lookup tables (LUTs) model for nanometer CMOS transistors is presented. A novel lookup-table (LUT) method, which is based on a multivariate Neville’s algorithm for the current-voltage (I-V) and Capacitance-voltage (C-V) characteristics of a transistor, is proposed for the simulation of MOS transistor circuits. The simulation speed is noted to be significantly enhanced with sufficient accuracy via a dynamic programming procedure with the implementation of the proposed approach compared to the current state of the art models. Simulation results are implemented in a 28-nm fully depleted SOI technology (FDSOI). Compared to simulations with both the BSIMSOI model and the Lagrange interpolation lookup table, the computation time of the proposed approach can be reduced by 8.X and beyond in transient analysis.

13:40-14:00

Basic Analog and Digital Circuits with a-IGZO TFTs

Pydi Ganga Bahubalindruni1, Vítor Tavares3, Pedro Barquinha2, Rodrigo Martins2 and Elvira Fortunato2

1IIITD, Okhla Industrial Estate, Phase III, New Delhi, India - 110020; 2CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa and CEMOP-UNINOVA, 2829-516 Caparica, Portugal; 3INESC TEC and Faculty of Engineering, University of Porto, Campus FEUP, Rua Dr. Roberto Frias, 378, 4200-465 Porto, Portugal

This paper presents the characterization of fundamental analog and digital circuits with a-IGZO TFTs from measurements performed at normal ambient. The fundamental blocks considered in this work include digital logic gates, a lowpower single stage high-gain amplifier with capcacitive bootstrapping and a level shifter/buffer. These circuits are important functional blocks in analog/Mixed signal IC design with oxide TFTs. Being fabricated at low temperature (< 200 °C), they can find potential applications in low-cost large-area flexible systems.

14:00-14:20

In-System IGBT Power Loss Behavioral Modeling"

N. Femia1, M. Migliaro1, C. Pastore2, D. Toledo1,2

1DIEM-University of Salerno, Via Giovanni Paolo II, n.132, 84084 FISCIANO (SA), ITALY; 2Whirlpool Corporation, Cassinetta di Biandronno (VA), ITALY

In high-power-density power electronics applica- tions, it is important to predict the power losses of semiconductor devices in order to maximize global system efficiency and avoid thermal damages of the components. When different effects influence the power losses, some of which difficult to be physically modeled, it is worthwhile to use empirical laws obtained starting from experimental data, like the Steinmetz’s equation widely used for inductors’ magnetic core losses prediction. This paper discusses a method to find empirical power loss models by using Genetic Programming (GP). In particular, the GP approach has been applied to identify power losses in Insulated Gate Bipolar Transistors for Induction Cooking application. A loss model has been obtained using an experimental training set, and the result has been successively validated.

14:20-14:40

A Verilog-A model of a silicon resistive strip for particle detectors

N. Franch1, O. Alonso1, A. Dieguez1, I. Vila2 and S. Hidalgo3

1Department of Electronics, University of Barcelona, Carrer Martí Franquès, 1. 08028-Barcelona, Spain; 2Instituto de Física de Cantabria IFCA (CSIC,UC), Edificio Juan Jordá, Avenida de los Castros, s/n E-39005 Santander (Spain); 3Centro Nacional de Microelectrónica (IMB-CNM,CSIC), Campus Univ. Autónoma de Barcelona 08193 Bellaterra, Barcelona (Spain)

This contribution describes the behavioral model for a silicon resistive strip for particle position tracking in particle colliders, focusing on its use in developing new integrated readout electronics.

14:40-15:00

Modeling of Fully Printed Organic Field Effect Transistors for Circuit Design and Simulation"

Olka Kaveh1,2,3, Bahman Kheradmand-Boroujeni1,3, Daniel Kasemann2, Karl Leo2 and Frank Ellinger1

1Chair for Circuit Design and Network Theory, Technische Universität Dresden, Dresden 01062, Germany; 2Institute for Applied Photo Physics, Technische Universität Dresden, Dresden 01062, Germany; 3Center for Advancing Electronics Dresden (cfaed),Technische Universität Dresden, Dresden 01062, Germany

Organic field effect transistors (OFETs) have significantly improved during recent years. However, there is still a lack of complete compact models for these devices, due to different materials, device structures, and manufacturing processes. Previous studies on compact OFET modeling have only considered static I-V characteristics, which are subject to the bias-stress effect. In this study, for the first time, two different large-signal OFET models are optimized to small-signal experimental data, which are less sensitive to the bias-stress effect. Li’s and Estrada’s models are studied overall I-V regions, from sub-threshold to above-threshold, and from linear to saturation region with unified formulations. It is found that Estrada’s model fits better to the trans-conductance, whereas the Li’s model fits better to the intrinsic gain. Both models are implemented in ADS circuit simulator, using the Verilog-A programming language. The bootstrapped amplifier is simulated and is compared with measurement data.

13:20-15:00 Design techniques for RF communications
Room 02.3
Chair: Okan Zafer Batur
13:20-13:40

Synthesis-Based Methodology for High-Speed Multi-Modulus Divider

Dimo Martev1, Sven Hampel2 and Ulf Schlichtmann1

1Institute for Electronic Design Automation, Technische Universität München, München-80333, Germany; 2Intel Germany, 47259 Duisburg

This paper presents the design flow for a radio frequency multi-modulus divider, located in a digital phase-locked loop, using a standard-cell library in 28 nm CMOS technology. The flow is based on VLSI tools for synthesis and automated place and route. The resulting design has a technology-independent fully behavioral description that allows fast translation to the next technology node. Being synthesizable, the divider is fully generic, VHDL as well as constraints, and can easily be modified and adapted for various applications and requirements. Presilicon verification based on sign-off static timing analysis shows operability of the design to up to 4.3GHz.

13:40-14:00

Miniaturized Dual-Band Balanced Antenna for LTE using Meander Lines"

I.T.E.Elfergani1, Abubakar Sadiq Hussaini1, Jonathan Rodriguez1 and R.A Abd-Alhameed2

1Instituto de Telecomunicações - Aveiro, Portugal; 2University of Bradford, Bradford, West Yorkshire, BD7 1DP, UK

A new compact dual-band balanced antenna is proposed with meandered lines operating in the LTE bands of 700/2600MHz. It has a compact size with the overall dimensioning of 54×18× 8 mm3, in which can be simply concealed within mobile handsets. Techniques such as meandered lines are used in order to accomplish a well- matching and size reduction of antenna. The meander lines were printed on FR4 substrate with relative permittivity of 4.4 and dielectric loss tangent of 0.0017 with a thickness of 1.6 mm. The results of the present design structure were checked in terms of reflection coefficient, operational bandwidth, current surface, and radiation pattern characteristics. The results have shown that the proposed design can be an attractive candidate for use in mobile handset.

14:00-14:20

Distributed Amplifier Design for UWB positioning systems using the gm over id methodology

G. Piccinni, G. Avitabile, G. Coviello and C. Talarico

1Electric and Information Department (DEI), Polytechnic of Bari, Bari, Italy, 70126; 2Department of Electrical and Computer Engineering, Gonzaga University, Spokane, WA 99258

In this paper we exploit the gm over ID methodology to optimize the design of a four stage conventional Distributed Amplifier (DA) for an Ultra-Wide Band positioning system. The W/L ratio and the DC-biasing of the amplifier’s transistors are determined according to the gm over ID methodology by using a series of lookup tables generated starting from the model of the devices. The DA was designed using the IHP 0.13 μm SiGe process and provides a 14 dB gain over a bandwidth of 10.6 GHz. The input/output return loss of the amplifier is lower than -17 dB over the entire bandwidth, with an average noise figure of 1.95 dB and a 26 mW DC-power consumption.

14:20-14:40

Compressed-Sampling-Based Behavioural Modelling Technique for Wideband RF Transmitter Leakage Cancellation System

Han Su, Ziming Wang and Ronan Farrell

Department of Electronic Engineering, National University of Ireland, Maynooth

A duplexer is necessary, but unfavourable for a frequency-division duplexing (FDD) base station, due to its bulky size, high cost and design challenges. In order to relax the performance requirement of such device, the transmitter (TX) leakage needs to be suppressed. The state-of-the-art solutions failed to provide a wideband solution for cancelling the TX leakage at RF frequency, due to the lack of delay optimization. Aiming to provide high delay estimation accuracy, this paper presents a modelling technique which is based on the compressed sampling matching pursuit (CoSaMP) algorithm for compressed sampling (CS). As a result, by using the proposed modelling technique, cancellation systems, particularly the ones that are based on the analog finite impulse response (FIR) filter structure, can be implemented to achieve wideband suppressing at RF frequencies.

14:40-15:00

MATLAB & VHDL-AMS Co-Simulation Environment for IR-UWB Transceiver Design

Okan Zafer Batur1, Günhan Dündar2 and Mutlu Koca2

1Department of Electrical and Electronics Engineering, Istanbul Bilgi University, Eyup, Istanbul, Turkey 34060; 2Department of Electrical and Electronics Engineering, Bogazici University,, Bebek, Istanbul, Turkey 34342

This paper presents a MATLAB-VHDL-AMS computer aided design automation flow for the design of an IR-UWB transceiver. The co-simulation environment helps the user to create the transceiver system in a top-down design methodology. The constructed CAD flow enables the user to analyze the performance of the system with the aid of BER vs EB /N0 figures. The effect of system and circuit level parameters on the system performance can be analyzed and these parameters can be determined from the model. The transceiver system model is based on circuit parameters such as gain, linearity, and reflection coefficient. The individual system blocks can be interchanged with actual circuit designs. Therefore, the performance of these individual blocks in a transceiver system can also be studied.